Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2000-06-09
2001-11-27
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S107000, C438S210000, C438S257000, C438S773000, C438S776000, C438S324000, C438S763000, C438S765000
Reexamination Certificate
active
06323097
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Filed of the Invention
The present invention relates generally to semiconductor integrated circuit manufacturing and more particularly to methods and structures for monitoring and controlling overlay and spacing.
(2) Description of Prior Art
As design rules shrink there are increased accuracy requirements for the alignment of features on successive wafer levels and for the separation of features on a single level; i.e. for overlay and spacing. To meet these requirements overlay and spacing need to be monitored and controlled. The prior art includes various electrical test structures and methods for this purpose. Resistive and van der Pauw bridges are used with features whose relative alignment is desired forming elements of the bridge. The bridge test structure is designed so that for exact alignment a null result is obtained; e.g. equal voltages across the features being compared. The degree of misalignment is ascertained by the difference in the voltage measured across the features. Voltages across features are often small, especially when their resistance is low. Differences in voltage across features needed to detect small misalignments are smaller yet. Thus special equipment and techniques are required to achieve the required sensitivity in the voltage measurements. In addition, elaborate test structures, testing procedures and algorithms are needed to extract quantitative misalignment results from measured voltages. Cresswell et al., in U.S. Pat. No. 5,383,136 disclose an electrical test structure and method for measuring the misalignment of conductive features on an insulating substrate. A bridge method is used and misalignment is proportional to the difference in voltage across features being compared. The test structure is designed so that effects of the test structure geometry can be measured and compensated for using a succession of test signals and inserting the measured response voltages in provided algorithms. These elaborate structures and procedures, as well as high precision voltage measurements are required to achieve the fine resolution needed for submicron design rules. U.S. Pat. No. 5,602,492 to Cresswell et al., a continuation-in-part of U.S. Pat. No. 5,383,136, teaches a method of eliminating random errors arising from imperfections. U.S. Pat. No. 5,617,340 to Cresswell et al. and U.S. Pat. No. 5,699,282 to Allen et al. are continuations-in-part of the above patents and involve methods for measuring misalignment, which require a multiplicity of test structures and a multiplicity of precision measurements. Buehler et al. in U.S. Pat. No. 4,918,377 teach a method of determining the reliability of conductors deposited on an uneven surface. The method involves measuring the resistance of a test structure in which the conductors are deposited over a multiplicity of steps.
SUMMARY OF THE INVENTION
Accordingly, it is a primary objective of the invention to provide simple test structures and methods for measuring overlay and spacing that could be achieved without resort to a multiplicity of measurements and to extreme precision. To achieve this objective ladder resistors are used. Traditionally, the dimension of a feature is inferred from the resistance of the feature. Thus, small differences in length correspond to small differences in resistance and the resolution of small differences requires precise resistance measurements. In the method of the invention, length is inferred from the ladder-rung dimension and from the number of rungs that have made electrical contact. The rungs are electrically in parallel and could have the same resistance so that a significant resistance difference exists if a rung has or has not made contact. There is therefor no need for very sophisticated resistance measurements.
Embodiments of the invention relate to measurement of the spacing of parallel conductive lines, which are on the same level of an integrated circuit semiconductor chip. Rungs of equal length, L and of equal resistance, r are disposed perpendicular to the lines and contacting one of the lines, the ladder reference line. A staircase pattern is constructed with its base along a neighboring line. The step facing a rung is closer to the ladder reference line then the step below it by a chosen distance, d that is a fraction of L. The resistance between the ladder reference line and the neighboring line is r
, n being the number of rungs making contact with the staircase pattern of the neighboring line. Then it can be inferred that the distance from the reference line to the nth step of the staircase pattern is between L−d and L. If the edge of the line corresponds to the mth step then the spacing between the ladder reference line and the neighboring line is between L+(m−n−1)d and L+(m−n)d. The total number of rungs, N, and r should be chosen so that r/N is an easily measured resistance. The lowest resistance to be encountered, resulting when all rungs make contact, is r/N. Spacing between features other than parallel lines can be accomplished in the same method as for parallel lines by appropriate replication and connection of the features. An alternative method of measuring the spacing of parallel lines on the same level of an integrated circuit semiconductor chip does not require a step pattern. Instead the rung length is incremented. The rung resistance can be arranged to be unaffected by the change in length by inserting a sufficiently large resistance in each rung. Then the situation is essentially the same as when equal rungs are used with a staircase pattern and the results are the same.
Other embodiments of the invention relate to misalignment of features on different levels. The case of parallel lines on adjoining levels, which should coincide for perfect alignment, is a typical situation; other situations can be treated similarly. Three parallel, equally spaced conducting lines are deposited on the first level. Staircase patterns are constructed along the inner edges of the outer lines, with step increment, d. An insulating layer, which separates the levels, is deposited; its upper surface defining the second level. A conductive line is deposited on the second level. For perfect alignment this line would coincide with the central line of the first level. Ladders are deposited on the second level, with conductive rungs of length L, and resistance r, emanating from both sides of the second level line. Vias had been opened through the insulating layer at the end of each rung so that the separation between the outer edge of the via and the end of the rung is much less than d, the incremental staircase distance. The vias had been filled with conductive material, preferably the same material as the lines, and they contact the second level ladders. Two resistances are measured, between the second level line and each of the outer first level lines. A measured resistance of r
between the second level line and an outer first level line indicates that the nth step of the staircase pattern of that fist level line is between L−d and L from the edge of the second level line. If the edge of the mth step corresponds to the edge of the line then the separation between the neighboring edges of the second level line and that first level line is between L+(m−n−1)d and L+(m−n)d. Let m and n be as defined for the first level line on the right, p and q the corresponding meanings for the first level line on the left. The second level lines are translated with respect to the first level lines by an amount which is between (m−n−p+q+1)d/2 and (m−n−p+q−1)d/2, with the translation being to the left for positive values and to the right for negative values. The spacing of the first level lines is between L+(m−n+p−q)d/2 and L+(m−n+p−q−2)d/2. Alternatively, instead of staircase patterns on the first level lines, the length of the rungs of the two second-level ladders can be incremented and the r
Lo Tseng Chin
Wu Shien-Yang
Young Konrad
Ackerman Stephen B.
Bowers Charles
Lee Hsien-Ming
Saile George O.
Taiwan Semiconductor Manufacturing Company
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