Electrical measurement of level-to-level misalignment in integra

Details Electrical measurement of level-to-level misalignment in integra Electrical measurement of level-to-level misalignment in integra

1980-07-11

1983-06-07

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 324158R, H01L 2166

Patent

active

043864597

ABSTRACT:
At least one chip on a multiple-chip integrated circuit wafer is dedicated for use as a test device for checking mask level-to-level misalignment. The test device is made during the same fabrication sequence in which the circuit-containing chips are made. No additional processing steps are required for the test device. By forming unique S-shaped members in each test device and establishing electrical contact therewith, a sensitive electrical tester is provided for indicating level-to-level registration in the circuit-containing chips.

REFERENCES:
patent: 3650020 (1972-03-01), Mar
patent: 3808527 (1974-04-01), Thomas
patent: 3835530 (1974-09-01), Kilby
patent: 3983479 (1976-09-01), Lee et al.
patent: 4144493 (1979-03-01), Lee et al.
patent: 4257825 (1981-03-01), Schaumberg
Russell et al., Internat. Electron Devices Meeting Techn. Dig., Dec. 5-7, 1977, Wa. D. C., Sect. 2.1, pp. 7A-7F.

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