Etching a substrate: processes – Forming or treating electrical conductor article – Forming or treating of groove or through hole
Patent
1994-10-17
1996-10-22
Powell, William
Etching a substrate: processes
Forming or treating electrical conductor article
Forming or treating of groove or through hole
216 33, 216 66, 216 67, 216 65, 505411, 505412, 505413, B44C 122, C03C 1500
Patent
active
055673309
ABSTRACT:
Electrical interconnect structures comprised of high temperature superconducting signal layers on a substrate bonded to one another or optionally to a base substructure containing power and ground planes and processes for their preparation are disclosed.
REFERENCES:
patent: 4474828 (1984-10-01), Young et al.
patent: 4751482 (1988-06-01), Fukuta et al.
patent: 4827327 (1989-05-01), Miyauchi et al.
patent: 4837609 (1989-06-01), Gurvitch et al.
patent: 4942142 (1990-07-01), Itozaki et al.
patent: 4954480 (1990-09-01), Imanaka et al.
patent: 4980339 (1990-12-01), Setsune et al.
patent: 5057877 (1991-10-01), Briley et al.
patent: 5087605 (1992-02-01), Hedge et al.
patent: 5159347 (1992-10-01), Osterwalder
patent: 5462762 (1995-10-01), Onuma et al.
Hung, L. S. et al, J. Appl. Phys., 66(1) (Jul. 1, 1989).
Siegal, M. P. et al, Physica C 172, 282-286 (1990).
Jia, C. L. et al, Physica C 175, 545-554 (1991).
E. I. Du Pont de Nemours and Company
Powell William
LandOfFree
Electrical interconnect structures and processes does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrical interconnect structures and processes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrical interconnect structures and processes will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2355992