Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2007-05-25
2010-10-26
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S467000, C438S600000, C257S530000
Reexamination Certificate
active
07820492
ABSTRACT:
An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal silicide layer is provided on the semiconductor substrate adjacent the pipe region. When a programming voltage is applied, the metal silicide undergoes a thermally induced phase transition in the pipe region. The eFuse has improved reliability and can be programmed with relatively low voltages.
REFERENCES:
patent: 6492670 (2002-12-01), Yu
patent: 6661330 (2003-12-01), Young
patent: 7015076 (2006-03-01), Chan et al.
patent: 2002/0182827 (2002-12-01), Abe et al.
patent: 2004/0087120 (2004-05-01), Feudel et al.
Miyashita Katsura
Toyoshima Yoshiaki
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Patton Paul E
Smith Zandra
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