Electrical detection of V-groove width

Details Electrical detection of V-groove width Electrical detection of V-groove width

2001-10-29

2003-05-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Groove formation

C438S271000

Reexamination Certificate

active

06558974

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to electrical detection of V-groove width during the fabrication of photosensitive chips, which create electrical signals from an original image, as would be found, for example, in a digital scanner or facsimile machine.
BACKGROUND OF THE INVENTION
In the context of document processing, a raster input scanner, or simply “scanner,” is a device by which an image on a hardcopy original, such as a sheet of paper, is converted to digital data. A common design for a scanner includes a linear array of photosites with corresponding circuitry to form a linear array of photosensors. Each photosensor in the array is adapted to output a signal, typically in the form of an electrical charge or voltage, of a magnitude proportional to or otherwise related to the intensity of light incident on the photosensor. By providing a linear array of these photosensors and causing the array to scan relative to the hard-copy original, each photosensor will output a sequence of charge signals resulting from the various gradations of dark and light in the image as the individual photosensors move through a path relative to an image.
In most low cost scanners, such as presently found in inexpensive facsimile machines, the most typical technology for creating such a scanner is the charge-coupled device, or CCD. For higher-quality applications, CMOS technology in one or more photosensor chips are used.
The number of photosites (and therefore photosensors) that can be packed onto a single chip or wafer is limited, and this, in turn, limits the image resolution that can be achieved with a single photosensitive array. Joining several of the smaller photosensor arrays together to form a longer array, and particularly, to form a full page width array with increased resolution along with the attendant simplification of the scanning system that this allows is desirable.
Arrays of photosites are typically formed from a plurality of generally rectangular substrates and these substrates are separated by dicing or other suitable means from one or more circular silicon wafers to form photosensitive chips. (The shape of substrates do not have to be rectangular. Other geometric shapes are also possible). The photosensitive chips are preferably assembled end to end in a collinear fashion to improve image quality and to form a full width array.
One method presently employed to produce photosensitive chips is the formation of aligned V-grooves in the semiconductor wafer. The V-grooves are preferably etched along the 111 plane of the silicon, which is the easy slip plane for stress relief or cracks. V-grooves are needed for proper dicing of the chips in regions very close to active circuits. If the proper V-groove width is not there for each chip during dicing, chipping damage may occur and this will cause yield problems or a reliability degradation problem in the final photosensor array. Only 100% visual inspection of all wafers catches all of these defects, or a 100% visual inspection of a sample of wafers might indicate that there is a problem. Visual inspection of every chip on every wafer is labor intensive and prone to human error. Therefore, there is a need for a new method and apparatus to inspect and evaluate V-groove widths on the semiconductor wafer.
SUMMARY OF THE INVENTION
The present invention provides an apparatus for detecting width of a V-groove on a semiconductor wafer including a plurality of V-groove legs, wherein each resistor leg comprises a diffusion layer etched on a silicon wafer, and wherein the resistor legs are spaced to overlap different chip areas and different areas upon which the V-groove is etched; a pad etched on the silicon wafer and coupled to the resistor legs; a tester supplying voltage to the pad after the V-groove has been etched into the silicon wafer; and apparatus coupled to the pad for determining the width of the etched V-groove. The diffusion layers are one of n-type or p-type. The pad is an input/output pad. The pad can be a separate test pad for testing V-groove width only. A pull up resistance is coupled to the pad and resistor legs, wherein said pull up resistance is much larger than each resistor leg, such that voltage division gives a digital output indicating whether each resistor leg has been opened by etching. The digital output associated with each resistor leg is added or processed to produce a representative digital or analog output proportional to the width of the V-groove.
The present invention provides a method for determining the width of a V-groove on a silicon wafer before dicing including defining a V-groove region on the silicon wafer; applying resistor legs within a test area on the silicon wafer; connecting the legs to a pad through metal layers and nodes; etching a V-groove in the silicon wafer in the V-groove region; applying one of a test voltage or test current to each resistor leg; calculating the resistance of the each leg after etching the V-groove in the silicon wafer; and calculating the width of the etched V-groove based on the resistance of each leg resistor.


REFERENCES:
patent: 6237399 (2001-05-01), Shivaram et al.
patent: 6342403 (2002-01-01), Hosier et al.
patent: 6396297 (2002-05-01), Hosier et al.

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