Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-05-26
2003-06-03
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S753000, C257S767000, C257S769000
Reexamination Certificate
active
06573599
ABSTRACT:
FIELD OF INVENTION
This invention relates generally to semiconductor devices. More particularly, the present invention relates to an improved electrical contact system for compound semiconductor devices, such as gallium arsenide (GaAs) devices, and a method of forming the same.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits include a plurality of microelectronic structures (e.g., transistors, diodes, and the like) formed by creating a variety of doped regions in a semiconductor wafer substrate. These regions are formed by performing a number of operations, for example, epitaxial growth, diffusion, ion implantation, etching, and the like. These devices are then interconnected by a conductive metallization layer to form a desired integrated circuit.
This invention concerns semiconductor devices that are manufactured by using a multilayer structure formed through the epitaxy of semiconductor materials of different properties and that are useful as ultrahigh frequency and ultrahigh-speed transistors. For example, applications of the present invention may be found in connection with P+ contacts to laser diodes, heterojunction bipolar transistors (HBTs), light emitting diodes (LEDs), Schottky diodes, field effect transistors (FETs), metal-semiconductor field effect transistors (MESFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), and other compound semiconductor and optoelectronic devices. For purposes of illustration only, and without limitation, the present invention will be described with particular reference to its application to the manufacture of gallium arsenide (GaAs)-based HBTs.
In recent years, high performance HBTs have been attracting much attention for power amplifier and high-speed digital applications, including such areas as automotive radar, traffic control, and wireless applications. The general structure of and conventional fabrication processes for HBTs are well known by those skilled in the art.
HBTs are made up of collector, base, and emitter layers disposed to form a pair of junctions. In general, an HBT is a three-terminal device in which the upper layers (i.e., the base and emitter layers) are etched away in order to expose the underlying collector layer. Contacts are made to each of the layers to provide the three-terminal device having a collector, emitter, and a base contact.
Prior art techniques typically include depositing a gold overlayer on the base contact to reduce the sheet resistance of the contact. However, although gold exhibits desirable electrical properties such as low resistivity and high conductivity, it has a tendency of inward diffusion even under moderate temperatures, which can negatively affect the performance characteristics of the electronic device. Use of diffusion barrier layers comprising refractory metals, such as tungsten, under the gold layer has been attempted in the prior art; however, such diffusion barriers are inadequate to prevent lateral “spillover” of gold and other reactive overlayer metals past the barrier layer during deposition, which results in undesirable and uncontrollable alloying and inward diffusion of these metals at the edge of the base contact.
The reliability of HBTs is directly related to the integrity of the ohmic contacts at the emitter, base, and collector layers. In particular, fabrication of base contacts with excellent ohmic characteristics, namely, low sheet resistance, is critical to achieving high-performance HBT integrated circuits. High performance HBTs are characterized by a heavily doped base and an ultra-thin base layer, generally having a thickness of less than about 500 angstroms. Because of this thin base layer, it is difficult to fabricate a direct contact between the base electrode and base layer that simultaneously reduces sheet resistance and does not alloy through the base layer due to lateral spillover.
Primary considerations in the choice of an ohmic metallization system are low specific contact resistance, thermal stability, good morphology, good adhesion to and very shallow penetration of the contact layer into the semiconductor, and resistance to wet chemical processing. The selected metallization system for the ohmic contacts must provide the correct electrical link between the active region of the semiconductor device and the external circuit, while at the same time enabling a low-energy carrier transport through the thin interface region and ensuring a negligible series resistance in it under normal device operating conditions. As is common in the art, the deposited ohmic contacts often are alloyed under relatively high-temperature conditions in order to drive the required metal-semiconductor interfacial reaction, or may experience high-temperature thermal cycles as may be required by subsequent processing steps in forming the integrated circuit. High-temperature alloy processes and/or thermal cycles may result in the formation of undesirable alloy “spikes” in the interfacial region of the ohmic contact and the underlying semiconductor layer. These spikes in the interfacial layers can lead to non-uniform current flow through the device and degraded microstructure.
Transmission Electron Micrographs (TEM) of HBTs manufactured by prior art techniques indicate formation of such submicroscopic spikes at the edge of the base contact, which are believed to be a consequence of “spillover” of excess gold and platinum at the contact edge that uncontrollably alloy with the underlying GaAs base layer during high-temperature alloy processing. These submicroscopic spikes may cause “punchthrough” of the base contact through the base layer and into the underlying collector layer. This punchthrough generally results in lower reliability and degraded performance of the semiconductor device.
Further disadvantages of prior art fabrication techniques for ultra-thin base layer HBTs include utilization of precious metals, such as gold and platinum, which increase raw material costs and which ultimately may degrade device performance characteristics, as discussed above. Additionally, as the number of metallization layers deposited to form the base contact structure increases, the cost of manufacturing the HBT device increases.
A method of forming contacts on thin base layer HBTs is thus needed that eliminates base contact punchthrough of reactive contact metallization, reduces raw material costs by eliminating and/or minimizing the use of precious metals, such as gold and platinum, and facilitates manufacturing by reducing the number of metallization layers in the contact structure, without sacrificing device performance and functionality. In particular, there exists a need in the art for a suitable ohmic contact for thin base layer HBTs that exhibits low sheet resistance, but that excludes reactive metal overlayers that have proven detrimental to the reliability and manufacturability of HBT devices of the prior art.
SUMMARY OF THE INVENTION
The present invention relates to an improved contact system for compound semiconductor devices, such as gallium arsenide (GaAs) devices, and a method of forming the same. In particular, one embodiment of the present invention relates to an improved contact system and method useful in the manufacture of P+ doped gallium arsenide (GaAs) heterojunction bipolar transistors (HBTs).
The present invention meets the aforesaid needs and solves the problem of base contact “punchthrough” by eliminating excess sources of reactive metal—such as platinum and gold—that may cause “spillover” at the contact edge. In accordance with a preferred embodiment of the present invention, a thin “reactive” layer of platinum or other suitable metal that alloys and makes good ohmic contact with the underlying P+ doped GaAs base layer is deposited on the base layer of a HBT. On this reactive layer, a cap layer of refractory metal or metallic compound is deposited, which serves as a current spreading layer. No additional overlayers of platinum or gold are necessary.
In accordance with a preferred em
Burton Richard S.
Canfield Philip C.
Fourson George
Pham Thanh
Skyworks Solutions Inc.
Thomas Kayden Horstemeyer & Risley LLP
LandOfFree
Electrical contact for compound semiconductor device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrical contact for compound semiconductor device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrical contact for compound semiconductor device and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3137403