Electrical connector with dual-function sidewalls

Details Electrical connector with dual-function sidewalls Electrical connector with dual-function sidewalls

2002-12-13

2004-02-24

Nguyen, Truc (Department: 2833)

Electrical connectors

Preformed panel circuit arrangement, e.g., pcb, icm, dip,...

With provision to conduct electricity from panel circuit to...

C439S342000, C439S525000, C439S885000, C439S330000

Reexamination Certificate

active

06695625

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrical connector for electrically connecting an electronic package such as a land grid array (LAG) chip with a circuit substrate such as a printed circuit board (PCB), and particularly to a connector having sidewalls that securely position the electronic package there between and that facilitate installation of terminals into the connector.
2. Description of the Prior Art
Land grid array (LAG) electrical connectors are widely used in the connector industry for electrically connecting LAG chips to printed circuit boards (PCBs) in personal computers (PCs). As described in “Nonlinear Analysis Helps Design LAG Connectors” (Connector Specifier, February 2001, pp. 18-20), the LAG connector mainly comprises an insulative housing and a multiplicity of terminals. The housing comprises a multiplicity of terminal passageways defined therein in a generally rectangular array for interferentially receiving corresponding terminals. Due to the very high density of the terminal array in a typical LAG chip, the LAG chip need to be precisely seated on the LAG connector to ensure reliable signal transmission between the terminals and the LAG chip. Means for accurately attaching the LAG chip to the LAG connector are disclosed in U.S. Pat. Nos. 4,504,105, 4,621,884, 4,692,790, 5,302,853 and 5,344,334.
Referring to
FIG. 4
, a conventional connector
6
comprises an insulative housing
60
and a multiplicity of terminals
61
received therein. In forming the connector
6
, a carrier strip (not shown) comprises a row of the terminals
61
, and a row of connecting sections
610
respectively connecting the terminals
61
with a main body of the carrier strip. The housing
60
comprises four raised sidewalls
62
, and a flat base
63
disposed between the four raised sidewalls
62
. The base
63
and the sidewalls
62
cooperatively define a space there between for receiving an LAG chip (not shown) therein. The base
63
defines a multiplicity of terminal passageways
64
for receiving the terminals
61
therein. When the LAG chip is seated on the LAG connector
6
, the four sidewalls
62
can securely engage the LAG chip there between. However, installation of terminals
61
into those passageways
64
near the sidewalls
62
is problematic. Once the terminals
61
have been inserted into such passageways
64
, the connecting sections
610
must be cut from their corresponding terminals
61
. Because the carrier strip is located close to the sidewalls
62
, there is insufficient space to manipulate the carrier strip to allow easy cutting off of the connecting sections
610
. Such manipulation is blocked by the sidewalls
62
, which is liable to sustain damage as a result.
FIG. 5
shows another conventional LAG connector
6
′ devised to overcome the above-described problem. The LAG connector
6
′ comprises a housing
60
′. The housing
60
′ comprises a flat base
63
′ and four raised sides
62
′ surrounding the base
63
′. Two opposite of the sides
62
′ each have a sloped surface that slants down toward the base
63
′. The sloped surfaces provide additional space to manipulate a carrier strip to allow easy cutting off of connecting sections
610
′ from their corresponding terminals
61
′. However, the sloped surfaces diminish the original advantage of the sides
62
′ being raised. That is, a reduced surface area of the sides
62
′ is available to retain the LAG chip there between. This can adversely affect the reliability of signal transmission between the terminals
61
′ and the LAG chip.
Therefore, a new LAG electrical connector which overcomes the above-mentioned problems is desired.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an electrical connector for electrically connecting an electronic package such as an LAG chip with a circuit substrate such as a PCBA, whereby the electrical connector can facilitate installation of terminals into a housing thereof.
Another object of the present invention is to provide an electrical connector having sidewalls that securely position an electronic package there between and that facilitate installation of terminals into the connector.
To achieve the above objects, an electrical connector in accordance with a preferred embodiment of the present invention is for connecting a land grid array (LAG) chip with a printed circuit board (PCB). The connector includes an insulative housing, and a plurality of terminals received in a plurality of passageways defined in the housing. The housing has a flat base and sidewalls extending upwardly from the base, the base and the sidewalls cooperatively defining a space there between for retaining the LAG chip therein. Two opposite of the sidewalls each define a multiplicity of evenly spaced recesses therein, thereby forming a multiplicity of evenly spaced projections.
When terminals are installed near the projections, a common carrier strip connecting the terminals is bent down so that connecting sections of the carrier strip are received in corresponding recesses. Junction portions between the terminals and their respective connecting sections are cut, and a main body of the carrier strip having the connecting sections is removed. The recesses enable the carrier strip to be manipulated so that sufficient space is made available for cutting off of the connecting sections without interfering with the sidewalls thereat. The projections provide precise fitting positioning of the LAG chip in the space. This ensures that engagement between the terminals and pins of the LAG chip is accurate and reliable.


REFERENCES:
patent: 3951495 (1976-04-01), Donaher et al.
patent: 4080032 (1978-03-01), Cherian et al.
patent: 4542949 (1985-09-01), Tewes et al.
patent: 4616895 (1986-10-01), Yoshizaki et al.
patent: 5066245 (1991-11-01), Walker
patent: 5493237 (1996-02-01), Volz et al.
patent: 5788510 (1998-08-01), Walker

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