Electrical circuit testing device and circuit comprising the sai

Details Electrical circuit testing device and circuit comprising the sai Electrical circuit testing device and circuit comprising the sai

1990-03-01

1991-01-01

Atkinson, Charles E.

Excavating

G01R 3128

Patent

active

049824031

ABSTRACT:
A device for the testing of electrical circuits and a circuit comprising the said device are disclosed. The testing device is used to test electrical circuits by the generation of test vectors and the compression of the signal at the output of the device to be tested. The device of the present invention uses the same shift register, certain cells of which are looped at the input, by means of an exclusive-OR logic gate, to generate test vectors and perform signature analysis. Thus it is possible to test electrical circuits themselves as well as the input/output buses. The invention can be applied, in particular, to the testing of computers, microprocessors, memories, fast Fourier transform calculators, adders, multipliers, combinational logic systems or circuits including combinational logic systems or circuits that have internal memorizing devices.

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Bhavsar et al., Self-Testing by Polynomial Division, 1981 Int'l. Test Conference, IEEE, pp. 208-216.
IBM Technical Disclosure Bulletin, vol. 25, No. 10, Mars 1983, pp. 4958-4960, New York, U.S.; P. S. Bottorff et al.: "Self-Testing Scheme Using Shift Register Latches".
IBM Technical Disclosure Bulletin, vol. 26, No. 3B, About 1983, pp. 1604-1606, New York, U.S.; D. A. Calvin: "Design for Self-Test SRL Implementation".
IBM Technical Disclosure Bulletin, vol. 26, No. 10B, Mars 1984, pp. 5566-5570, New York, U.S.; A. Blum: "Self-Testing Mechanism".

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