Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
2001-07-09
2003-03-25
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S283000, C327S284000
Reexamination Certificate
active
06538487
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cascade connection type inverter circuit used in a semiconductor integrated circuit. Additionally, the present invention relates to a limiting amplifier using a cascade connection type inverter circuit in an input stage thereof.
2. Description of the Related Art
A conventional input circuit of a limiting amplifier is disclosed in “General Meeting of the Electronic Information Communication Society, Lecture Documents C-10-29”, (1998).
FIG. 2
is a view showing a conventional example of the inverter circuit used in the above input circuit of the limiting amplifier. Note that the above document explains a case in which a GaAs MESFET (a metal semiconductor FET) is used as a semiconductor element constituting the inverter circuit and a DCFL (direct coupled FET logic) is used as a basic logic circuit.
In
FIG. 2
, an input signal is input from a third input terminal. The third input terminal is connected to a mid-point of the connection between an input terminal of a fourth inverter INV
4
, which constitutes a first stage, and one of the electrodes of a sixth resistor R
6
, which constitutes an end terminal. The other electrode of the sixth resistor R
6
is connected to a mid-point of the connection between one of the electrodes of the second capacitor C
2
and one of the electrodes of a seventh resistor R
7
. The other electrode of the seventh resistor R
7
is connected to an output terminal of the sixth inverter INV
6
, which constitutes the last stage. The output terminal of the fourth inverter INV
4
is connected to the input terminal of the fifth inverter INV
5
. The output terminal of the fifth inverter INV
5
is connected to the input terminal of the sixth inverter INV
6
.
FIG. 3
shows a circuit structure of the fourth inverter INV
4
, the fifth inverter INV
5
and the sixth inverter INV
6
. Each of these inverters uses a depletion-type FET (referred to as D-FET hereinafter) in the load thereof while an enhancement type FET (hereinafter referred to as E-FET) is used in the switching portion thereof. Note that a drain electrode of the first D-FET
1
, which constitutes the load, is connected to the second power source supply terminal. Furthermore, the gate electrode of the first D-FET
1
and the source electrode thereof are short-circuited. At the same time, the gate electrode and the source electrode are connected to the drain electrode of the second E-FET
2
, which functions as the switching portion, and to the second output terminal, which constitutes the output of the inverter. For reference, the gate electrode of the second E-FET
2
is connected to the second input terminal, which constitutes the input of the inverter. Furthermore, the source electrode of the second E-FET
2
is grounded.
In the inverter circuit shown in
FIG. 2
, the input signal, which is input via the third condenser C
3
, is propagated via the fourth, fifth, and sixth inverters INV
4
to INV
6
so as to approach the logic level of the basic logic circuit, and is then output.
Note that, in an inverter circuit having this type of configuration, a high loop gain can be obtained with the serial connection of the fourth inverter, the fifth inverter and the sixth inverter INV
4
to INV
6
. Consequently, when the output signal is fed back to the input side via the seventh resistor R
7
, the logic threshold value of the fourth inverter INV
4
and the central voltage of the amplitude of the input signal can be matched with each other. When the central voltage of the amplitude of the input signal and the logic threshold value of the inverter match each other, it becomes possible to maintain on an equal level the duty ratio, which is a time ratio between the high level of the input signal and the low level thereof.
However, in a conventional input circuit, when the amplitude of the input signal increases at the time when the input signal is a high level signal, a Schottky current flows out between the gate and the source of the switching FET (E-FET
2
) of the fourth inverter INV
4
, which has the effect of lowering the voltage which appears in the third input reference voltage. This leads to the generation of a disparity between the central voltage of the amplitude of the input signal and the logic threshold value of the fourth inverter INV
4
.
After this type of high level signal, which causes a Schottky current to flow out in this way has been input, the central voltage of the amplitude of the input signal is lowered with the result that the low level of the input signal becomes lower than the original low level (a voltage which is lower by ½ of the amplitude of the input signal from the logic amplitude of the fourth inverter INV
4
).
The lowering of this voltage leads to a change in the duty ratio in the signal that is applied to each of the inputs of the fifth inverter INV
5
and the sixth inverter INV
6
. As a consequence, there arises a problem in that the duty ratio output from the sixth inverter INV
6
will be greatly changed as compared with the duty ratio of the input signal.
Furthermore, in a conventional circuit, when the duty ratio of the signal output from the sixth inverter is controlled, it is necessary to directly control the third input reference voltage. However, there is a problem that this type of highly sensitive and stable control are difficult when this type of control is performed.
The present invention has been made in consideration of the issue (problem) described above. An object of the present invention is to provide a cascade connection type inverter circuit that is capable of obtaining an output signal exhibiting little change in the duty ratio with respect to the input signal as compared with the conventional art, and which can be controlled in a highly sensitive and stable manner even when the duty ratio is controlled. A further object of the present invention is to provide a limiting amplifier having excellent input and output characteristics by using this type of cascade connection type inverter circuit.
SUMMARY OF THE INVENTION
In order to solve the problems described above, according to a first aspect of the present invention, there is provided a cascade connection type inverter circuit in which the inverters at odd-numbered stages are connected in a cascade manner, and an output of the inverter at the last stage is fed back to the input circuit of the inverter at the first stage via an impedance element, the circuit being characterized in that the connection described below is adopted.
Namely, a switching means is connected between the output terminal and the input terminal of the inverter at the first stage, the switching means supplying to an input circuit of the inverter at the first stage a compensation current for compensating a disparity between the logic threshold value of the inverter at the first step and the central voltage of the input signal thereof when the voltage generated between the output terminal and the input terminal of the inverter at the first stage exceeds a predetermined threshold value. Here, it is desirable to use transistors and diodes as the switching means.
With the adoption of this type of configuration, when the voltage generated between the output terminal and the input terminal exceeds a predetermined threshold value, for example, when the level of the signal applied to the input terminal is “L”, and the level of the signal appears at the output terminal is set to “H”, the central voltage of the input signal, which was lowered under the influence of the current following when the level of the signal applied to the input terminal is set to “H” and the level of the signal that appears at the output terminal is set to “L,” can be raised back to the original voltage by the compensation current provided by the switching means.
As a consequence, changes in the duty ratio that appear in a signal waveform that is propagated at each inverter stage can be minimized, and the change in the duty ratio can be restricted to a low level for the output signal wave
Murayama Hidehisa
Yamada Hiroyuki
Electric Industry Co. Ltd.
Rabin & Berdo P.C.
Wells Kenneth B.
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