Electric power conversion systems – Current conversion – Using semiconductor-type converter
Reexamination Certificate
2000-10-19
2002-06-11
Patel, Rajnikant B. (Department: 2838)
Electric power conversion systems
Current conversion
Using semiconductor-type converter
C327S108000, C318S811000
Reexamination Certificate
active
06404659
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electric power conversion apparatus, and more specifically to an electric power conversion apparatus having a circuit on a low side for performing a switching operation based on reference potential, and a circuit on a circuit on a high side for performing a switching operation based on floating reference potential.
2. Description of the Related Art
FIG. 1A
shows an example of an electric power conversion apparatus for converting a direct current into a three-phase alternating current in the conventional technology.
In
FIG. 1A
, semiconductor switches Q
11
through Q
13
and semiconductor switches Q
21
through Q
23
are configured by, for example, an IGBT (insulated gate bipolar transistor), perform a switching operation depending on the control of drive circuits
11
through
13
and drive circuits
21
through
23
, convert a direct current voltage into a three-phase alternating current, and provide it for a three-phase motor
36
.
With the configuration the semiconductor switches Q
21
through Q
23
and the drive circuits
21
through
23
perform a switching process using a ground level as reference potential. Therefore, they are referred to as a circuit on a low side circuit. On the other hand, since the semiconductor switches Q
11
through Q
13
and the drive circuits
11
through
13
perform a switching operation using the potential at terminal U, V, and W (fluctuating potential) as reference potential, they are referred to as a circuit on a high side. In the description below, the reference potential of the circuit on the low side is simply-called ‘reference potential’ while the reference potential of the circuit on the high side is called ‘floating reference potential’.
A control unit
30
is configured by, for example, a CPU (central processing unit), ROM (read-only memory), RAM (random access memory), etc., controls each drive circuit through an I/F (interface)
35
, and stops the operations of each drive unit when an alarm signal informing that an abnormal condition occurs is issued from each drive circuit.
The I/F
35
serves as an interface for information with the circuit on the low side and the control unit
30
, and also serves as an interface for information with the circuit on the high side and the control unit
30
(described later).
FIG. 1B
shows an example of a detailed configuration of the drive circuits
11
and
21
shown in FIG.
1
A and the peripheral units.
As shown in
FIG. 1B
, the drive circuit
11
includes a power supply monitor unit
11
a
, an abnormal condition detection unit
11
b
, an I/F
11
c
, and a driver
11
d
. The drive circuit
21
is similarly configured.
The power supply monitor unit
11
a
determines whether or not the power supply voltage provided for the drive circuit
11
is in a normal range, and notifies the control unit
30
of the determination result through the I/F
11
c
if it determines an abnormal condition.
The abnormal condition detection unit
11
b
monitors the electric current flowing through the semiconductor switch Q
11
, and the temperature of the semiconductor switch Q
11
, and notifies the control unit
30
through the I/F
11
c
when an excess current flows through the semiconductor switch Q
11
, or when the semiconductor switch Q
11
is overheating.
The I/F
11
c
cooperates with the I/F
35
for the consistency of physical properties so that information can be transmitted and received between the drive circuit
11
whose reference potential is not constant (that is, fluctuates depending on the status of an output) and the control unit
30
whose ground level is reference potential.
The driver
11
d
drives the semiconductor switch Q
11
according to the control signal provided from the control unit
30
through the I/F
11
c.
The drive circuit
21
has the similar configuration with the exception of a power supply monitor unit
21
a
. That is, since the drive circuits
11
through
13
have different reference potential, it is necessary to individually detect the power supply to be provided for each drive circuit. On the other hand, all of the drive circuits
21
through
23
have the ground level, only one power supply monitor unit has to be provided for one of the drive circuits
21
through
23
. In this example, only the drive circuit
21
is provided with the power supply monitor unit
21
a.
FIG. 1C
shows the details of the portion for transmitting alarm signals of the I/F
11
c
and the I/F
35
.
As shown in
FIG. 1C
, the portion for transmitting an alarm signal of the I/F
11
c
includes a P-channel MOS type FET
11
ca
, an inverter
11
cb
, and a power source
11
cc
. The power source
11
cc
is equivalent to an externally provided power source.
The portion for transmitting an alarm signal of the I/F
35
includes a power supply
35
a
, an inverter
35
b
, and a resistor
35
c.
FIG. 1D
shows in detail the circuit of the portion for transmitting control signals of the I/F
11
c
and the I/F
35
.
As shown in
FIG. 1D
, the portion for transmitting a control signal of the drive circuit
11
includes a resistor
42
and an inverter
43
. The resistor
42
is connected to the plus terminal of the I/F
11
c
, and the output of the inverter
43
is connected to the driver
11
d.
The portion for transmitting a control signal of the I/F
35
includes an inverter
40
, and an N-channel MOS type FET
41
. The input of the inverter
40
is connected to the control unit
30
, and the output is connected to the gate of the N-channel MOS type FET
41
. The source of the N-channel MOS type FET
41
is grounded, and the drain is connected to the input terminal of the inverter
43
.
Described below are the operations according to the above mentioned conventional technology. In the following explanation, the operations of the portion for transmitting the control signal shown in
FIG. 1D
are described first, and then the operations of the portion for transmitting the alarm signal shown in
FIG. 1C
are described.
First, the operation of the portion for transmitting a control signal is described below by referring to FIG.
1
D.
When a control signal is issued from the control unit
30
to the inverter
40
, the N-channel MOS type FET
41
enters an ON or OF state depending on the output of the inverter
40
. When the output from the control unit
30
indicates the H state, the output from the inverter
40
indicates the L state, and the N-channel MOS type FET
41
enters the OFF state. If the N-channel MOS type FET
41
enters the OFF state, the input of the inverter
43
indicates the H state. Therefore, the output of the inverter
43
indicates the L state, and the driver
11
d
drives the semiconductor switch Q
11
depending on the state and drives the semiconductor switch Q
11
(for example, sets the semiconductor switch Q
11
in the OFF state)
On the other hand, when the output from the control unit
30
indicates the L state, the output of the inverter
40
indicates the H state, and the N-channel MOS type FET
41
enters the ON state. When the N-channel MOS type FET
41
enters the ON state, the input of the inverter
43
indicates the L state. Therefore, the output of the inverter
43
indicates the H state, and the driver
11
d
drives the semiconductor switch Q
11
depending on the state (for example, sets the semiconductor switch Q
11
in the ON state).
In the above mentioned process, the semiconductor switch Q
11
can be appropriately controlled. Other semiconductor switches can also be switched in the similar operations.
The circuit shown in
FIG. 1D
can be replaced with the circuit shown in FIG.
1
E.
In this example, a source grounding circuit includes N-channel MOS type FETs
45
and
46
, and load resistors
47
and
48
. The output of the load resistors
47
and
48
are respectively input to the S terminal and the R terminal of a flipflop
49
. The output of the flipflop
49
is input to the driver
11
d
, and an on-pulse and an off-pulse are respectively provided for the N-channel MOS type FETs
Fuji Electric & Co., Ltd.
Greer Burns & Crain Ltd.
Patel Rajnikant B.
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