Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1999-08-17
2001-12-04
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S351000, C257S357000, C257S347000, C257S365000
Reexamination Certificate
active
06326642
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to matrix devices which have a matrix structure, have MOSFETs or MISFETs (collectively referred to as MOS devices) as switching devices, and perform dynamic operation such as liquid-crystal displays and dynamic RAMs (DRAMs). Examples of these matrix devices include electro-optical display devices and semiconductor memories. The invention also relates to a circuit for driving such matrix devices. More particularly, the invention relates to a device using thin-film transistors such as thin-film transistors formed as MOS devices on an insulating substrate.
BACKGROUND OF THE INVENTION
Recently, researches have been carried out on insulated-gate semiconductor devices comprising active layers (also known as active regions) in the form of thin films on an insulating substrate. Especially, thin-film insulated-gate transistors, or so-called thin-film transistors (TFTs) have been earnestly investigated. These devices are intended to be used to control pixels on a display device having a matrix structure such as a liquid-crystal display. They are classified into amorphous silicon TFTs or polysilicon TFTs according to the used semiconductor material and the state of the crystal. Also, researches have recently been made on materials showing a condition intermediate between polysilicon and amorphous state. These materials are called semi-amorphous materials and considered as an amorphous structure in which crystallites are floating. This kind of material is an excellent one combining both high mobility of a single-crystal condition and low leakage current of an amorphous state, as described later.
Furthermore, polysilicon TFTs are used on an integrated circuit of single-crystal silicon. This is known as SOI (silicon-on-insulator) technique. For example, these TFTs are used as load transistors in an SRAM of large scale integration. In this case, however, amorphous silicon TFTs are quite rarely employed.
A semiconductor circuit on an insulating substrate can operate at a quite high speed because conductive interconnects are not capacitance-coupled to the substrate. A proposal has been made to use semiconductor circuits of this kind as ultrahigh-speed microprocessors and ultrahigh-speed memories.
Generally, amorphous semiconductors have low field mobilities and thus cannot be used in those TFTs which are required to operate at high speeds. Also, P-type amorphous silicon has an extremely low field mobility and so it is impossible to fabricate P-channel TFTs, or PMOS TFTs. Therefore, it is impossible to fabricate complementary MOS (CMOS) circuits by combining P-channel TFTs, or PMOS TFTs, and N-channel TFTs, or NMOS TFTs.
However, TFTs fabricated from an amorphous semiconductor have the advantage that they have low OFF current. Hence, these TFTs are used in applications where very high speed operation is not required, only one conductivity type suffices, and electric charge must be held well, such as active-matrix transistors of a liquid-crystal device.
On the other hand, polycrystalline semiconductors have larger field mobilities than amorphous semiconductors and hence are capable of high-speed operation. For example, TFTs using a silicon film recrystallized by laser annealing show a field mobility as high as 300 cm
2
/V·s, which is very much large like field mobility of about 500 cm
2
/V·s of MOS transistors formed on a normal single-crystal silicon substrate. The operating speed of a MOS circuit on a single crystal of silicon is limited by the parasitic capacitance between the substrate and the conductive interconnects. In contrast, in case of the polycrystalline semiconductors (the recrystallized silicon film), such restrictions do not exist because the circuit lies on an insulating substrate. Consequently, an extremely high-speed operation is expected.
PMOS TFTs can be fabricated from polysilicon similarly to NMOS TFTS. Therefore, CMOS circuits can be formed. For example, active-matrix liquid-crystal displays having a so-called monolithic structure, i.e., not only the active-matrix portions but also peripheral portions such as drivers are fabricated from CMOS polycrystalline TFTs, are known.
TFTs used in the aforementioned SRAMs are formed, taking account of this point. PMOS devices are fabricated from TFTs and used as load transistors.
In normal amorphous TFTs, it is difficult to form source/drain regions by a self-aligning process as used in single-crystal IC fabrication techniques. Parasitic capacitance due to geometrical overlap of the gate electrodes and the source/drain regions presents problems. In contrast, polycrystalline TFTs can make use of a self-aligning process and, therefore, parasitic capacitance can be suppressed greatly.
Although polysilicon TFTs have features described above, some problems have been pointed out. In a general polysilicon TFT, an active layer is formed on an insulating substrate. A gate-insulating film and gate electrodes are formed on the active layer. This structure is known as the coplanar type. Though this structure can utilize a self-aligning process, it is difficult to reduce the leakage current (OFF current) from the active layer.
The causes of this leakage current are not fully understood but a major cause is due to interface-trapped charges created between the underlying base and the active layer. Accordingly, the problems of the leakage current are solved by fabricating the interface with meticulous care and reducing the interface trap density to such an extent that it is almost equal to the density at the interface between the gate-oxide film and the active layer.
In particular, in a high-temperature process (the highest process temperature is on the order of 1000° C.), a substrate is fabricated from quartz. A coating of silicon is formed on the substrate and thermally oxidized at about 1000° C. to form a clean surface. Then, an active silicon layer is formed by low-pressure CVD or other method.
In a low-temperature process (the highest process temperature is lower than 650° C.; also known as an intermediate-temperature process), a silicon oxide film having an interface trap density as low as that of the gate-insulated film is formed as a base film between the substrate and the active layer. Sputtering is an excellent method of forming the silicon oxide film. Oxide films having excellent characteristics can also be derived by ECR CVD or plasma-assisted CVD of TEOS.
However, it has been still impossible to reduce the leakage current. Especially, the leakage current from the NMOS was greater than that of the PMOS by one order of magnitude or more. We have conjectured that weak N-type of the active layer causes this great leakage current. In practice, we have observed with high reproducibility that the threshold voltages of PMOS and NMOS devices manufactured by high-temperature and low-temperature processes shift in the negative direction. Especially, in the case of high-purity silicon not doped with any other dopant, we have also inferred that the active layer becomes a weak N type in case of poor crystallinity being obtained as in the case of amorphous silicon. Polycrystalline silicon fabricated by a high-temperature process contains numerous lattice defects and dangling bonds unlike a perfect single crystal of silicon. These become donors and supply electrons. Of course, the possibility of the effect of a trace amount of impurity elements such as sodium remains.
In any case, if any one of the above-described causes exists, then we can explain away the above phenomena, i.e. NMOS devices have much lower threshold voltages and a larger amount of leakage current than PMOS devices. This is illustrated in
FIGS. 1
, (A)-(B). As shown in FIG.
1
(A), the N
+
source
12
of an NMOS is grounded. A positive voltage is applied to the N
+
drain
13
. Under this condition, if a voltage higher than the threshold voltage V
th
of a gate electrode
11
is applied to it, then a channel is formed on the side of the gate electrode of an active layer
14
, and a drain current flows as indicated by the
Takemura Yasuhiko
Yamazaki Shunpei
Abraham Fetsum
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
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