Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1998-12-01
2001-02-20
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S091000
Reexamination Certificate
active
06191631
ABSTRACT:
TECHNICAL FIELD
The invention relates to an electric circuit comprising at least one so- called switched capacitor. The invention furthermore relates to a method of operating such an electric circuit.
The invention is concerned specifically with an electric circuit comprising at least one switched capacitor which is switched via a parallel circuit having two electronic complementary switches controlled by complementary switching pulses, said circuit comprising a switching signal generator receiving a basic clock signal and generating therefrom a first switching pulse train as well as an almost complementary second switching pulse train. Moreover, the invention is concerned with a method of operating such an electric circuit.
BACKGROUND OF THE INVENTION
It is known in integrated circuits to realize specific functions with the aid of so-called switched capacitors (SC), for instance the function of an ohmic resistor. As is known, the impedance of a capacitor is calculated fiom the reciprocal value of the product of frequency and capacitance. Accordingly, for simulating ohmic resistors, integrated capacitors are controlled via switches, so that a continuous reloading operation takes place at the capacitor. The frequency of the control signal is matched to the capacitance of the capacitor such that the desired impedance is obtained.
By simulating ohmic resistors with the aid of switched capacitors, considerable chip area savings can be achieved.
For switching a “switched capacitor”, an insulated gate field effect transistor (IGFET) is usually employed, and in particular two complementary field effect transistors (CMOS field effect transistors) connected in parallel to each other are employed.
SUMMARY OF THE INVENTION
The present invention deals with problems in controlling a switched capacitor having complementary transistor switches controlled by complementary switching pulse trains.
FIG. 1
a
shows a switched capacitor C
s
comprising a first switching transistor
1
controlled by a switching signal øn and having a second switching transistor connected thereto which is complementary to the first switching transistor and controlled by a complementary switching signal øp. By the complementary control of the complementary transistors, both transistors are either simultaneously closed or simultaneously opened.
FIG. 1
b
shows a schematic diagram of a circuit within an integrated circuit comprising a switched capacitance C
s
having a transistor switch connected upstream thereof and a transistor switch connected downstream thereof each. Following the switched capacitance is an operational amplifier. The circuit shown in
FIG. 1
a
corresponds to the switching capacitance C
s
along with the switch connected upstream thereof which is controlled by switching pulse train ø, with ø in
FIG. 1
b
comprising both signals øn and øp. The switch shown in
FIG. 1
b
, which is controlled by signal ø, can be designed in similar manner as the parallel circuit of two complementary MOS field effect transistors shown in
FIG. 1
a.
FIG. 1
a
shows in broken lines parasitic capacitances C
n
and C
p
. These parasitic capacitances are constituted by the gatesourcc capacitance of the first switching transistor
1
and the second switching transistor
2
, respectively. When these two parasitic capacitances C
n
and C
p
have the same value and simultaneous blocking and simultaneous opening of the transistor switches
1
and
2
takes place, capacitor C
s
charges or discharges in the predetermined manner, respectively. However, an offset voltage arises at capacitor C
s
when the two capacitances C
n
and C
p
are different from each other:
Δ
Q
pn
=
(
C
p
-
C
n
)
Δ
U
=
Δ
C
pn
·
Δ
U
Δ
C
pn
=
0
}
Δ
Q
pn
=
0
(} means: from which follows)
From the above equation, a residual charge of 0 results for C
s
when C
p
has the same value as C
n
, whereas otherwise a residual charge different from 0 results. The above influence of the parasitic capacitances C
n
and C
p
is also referred to as “clock feedthrough”.
A further factor affecting the exact operation of the switched capacitor is the so-called charge transfer which arises due to the fact that the switching time on opening and closing of the two switching transistors
1
and
2
in
FIG. 1
is different for the two switching transistors.
FIG. 3
shows in the upper part the signal patterns for the switching pulses øn and øp, respectively, and it can be seen therefrom that in practical application the signal edges are not perpendicular to the time axis, but extend in oblique manner. In the lower part of
FIG. 3
, the output voltage V
out
of the switching arrangement according to
FIG. 1
a
is shown. In the ideal case, the output voltage V
out
at capacitor C
s
should retain the previous value after switching over of the two switching transistors
1
and
2
. However, in reality an offset (offset voltage) results, having the value &Dgr;U
cs
=&Dgr;Q/C
s
.
This offset voltage is due to different switching thresholds of the two switching transistors
1
and
2
(or of the n-channel or p-channel in case of a CMOS field effect transistor).
As can be seen from the top of
FIG. 3
, the descending edge of switching pulse on reaches the switching time according to threshold voltage V
Tn
earlier than the switching time of switching transistor
2
, with respect to which the switching signal øp reaches the threshold value V
Tp
relatively late.
FIG. 4
shows the circuit according to
FIG. 1
b
for the moment of time depicted in FIG.
3
. At first, switching transistor
1
closes in the course of the trailing edge of signal on, so that the resistance of this switch Roffn is very high (the resistance between drain and source of switching transistor
1
).
Due to the fact that the lower switching transistor
2
is not yet closed, the on-resistance Ronp (the resistance between drain and source of switching transistor
2
) still is much lower than the off resistance Roffn of first switching transistor
1
.
The following situation now results for the then effective parasitic capacitances:
Between the gate of switching transistor
1
and the output node of the circuit, there is a capacitance C
CFN
(CF stands for “clock feedthrough”). Between the gate of lower switching transistor
2
and the output node of the circuit, a capacitance of
C
CFP
+C
CTP
results (wherein CT stands for “charge transfer”).
While in the channel of switching transistor
1
no more charge is stored, no compensation of the charge stored in the p-channel of switching transistor
2
takes place. The residual charge thus is calculated as follows:
Δ
Q
=
(
C
CT
+
C
CFP
)
V
TN
-
C
CFN
·
V
TN
≈
C
CT
·
V
TN
In order to avoid the offset voltages arising due to the above processes and facts, the present invention suggests to regulate or control the edges of the switching pulse trains in such a manner that a complete compensation (when disregarding a remaining regulating deviation) of the offset voltage is obtained.
The invention to this end provides a method of operating a circuit comprising a switched capacitor, in which at least the leading edge and/or the trailing edge preferably of at least one of the complementary switching pulses (e.g., øn) can be controlled in such a manner that it is shifted in accordance with the output voltage of the switches (
1
,
2
) arranged in parallel with respect to the associated edge of the other one of the complementary switching pulse signals (øp). The electronic switches are preferably complementary MOS-FETs.
Such edge regulation or control is conceivable in the form of an alteration of the edge steepness. However, this is possibly difficult to realize in terms of circuit technology. The edge to be controlled therefore is shifted in time, in such a manner that both switches reach the blocking state virtually at the same
Kirchlechner Peter
Lubbe Jurgen
Schambacher Jorg
Galanthay Theodore E.
Iannucci Robert
Nguyen Linh
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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