Electric arc synthesis for arc detector testing and method...

Electricity: measuring and testing – Electromechanical switching device – Circuit breaker

Reexamination Certificate

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Reexamination Certificate

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06781381

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electrical circuit testing generally and more specifically to testing of arc detectors, circuit interrupters or circuit breakers.
2. Description of the Related Art
Arc detection in electrical circuits is important for both safety and reliability purposes. In some critical applications, such as circuits near flammable fluids, electrical arcing foreshadow or immediately cause disastrous consequences. For example, arcing has been suspected as the cause of several major airline crashes, resulting in tragic loss of life and major economic damages.
Numerous electrical arc protection devices have been developed ranging from the traditional fuse to sophisticated circuits utilizing digital signal processing techniques. Arc detection systems have also been developed in AC power systems and include monitoring the power waveform for wideband high frequency noise and examining the detected noise to find patterns of variation synchronized to the power waveform. See for example, U.S. Pat. No. 5,729,145 to Blades (1998); Blades includes a survey of prior art arc detection patents. High frequency noise monitoring methods do not allow the monitoring system to respond to frequency components of the arc signature that may lie in the general frequency range of the AC fundamental. Furthermore, false alarms are not precluded by such methods, which still respond to harmonics of the AC fundamental, whether or not arc related.
Some previous methods (including that of the Blades Pat. No. 5,729,145) require that the spectrum of the arc signature be correlated to line frequency fundamentals. Such methods do not adequately detect more chaotic arc signatures, and they are plagued by false alarms related to transient load conditions, which are often well correlated to line frequencies.
As a result of the number of new arc detection devices and problems with false alarms, there is a need for an efficient method by which arc detection devices can be objectively tested and qualified under circumstances that simulate “real-world” conditions. The simulation of electrical arcs is made difficult by the uncontrolled, chaotic nature of the physical phenomenon of the arc. Many distinct types of arcs are known to occur, having different physical and electrical characteristics. Ideally, a testing method should be well controlled but capable of duplicating a wide variety of electrical arc “signatures” in a repeatable fashion. It should test the arc detection device both for its capability to detect arcs and for its predilection for false alarms. It should be easily updated with new standards and knowledge, and it should allow thorough testing at moderate cost.
Some conventional approaches to arc simulation are crude. For example, a (multiconductor) cable can be sliced by a razor in a Guillotine-like test jig. Other mechanical methods have been proposed, including dripping saline solution onto neighboring conductors, or inducing thermal insulation failure. These methods are messy, inconvenient, and are not quantitative or reproducible.
There are also arcing conditions/variations that are difficult to simulate using these relatively crude testing methods. For instance propagation of an arc through the lines of a system can change the arc signal's characteristics, particularly at high frequency. The characteristics of an arc signal can change with the impedance of the unit under arc simulation test. When an arcing signal passes down a particular line, it can cause a signal to be generated in a proximal line, which is extremely difficult to simulate using conventional methods. Varied loads can also impact the arcing signal's characteristics, which is important because one focus of arc testing is to prove no false trips under load. Combining different condition permutations requires each condition to be individually embodied in the test equipment, which is both cumbersome and expensive. Change in the frequency of the system can have significant impact on the device under test. Most of these variations are simply impractical to simulate using conventional arc simulators.
Recently, efforts have been undertaken to capture arcing waveforms so that the arcing phenomenon can be studied and better understood. A number of waveforms have been captured and stored in digital form, and have been analyzed and catalogued. Some of the entities who capture, analyze and catalogue arc waveforms include the Boeing Company, the Navy, the Federal Aviation Administration (FAA) and Texas Instruments Incorporated.
SUMMARY OF THE INVENTION
The present invention seeks to provide a method and apparatus for reproducing an electrical signal, which controllably simulates the electrical conditions that accompany electrical arcing. The invention also includes a system and method of testing the response devices such as arc detectors, circuit interrupters or circuit breakers electrical, to arcing conditions.
One embodiment of the invention comprises a system for synthesizing electrical arcs for arc detector testing using the arc's captured current and voltage waveforms. A voltage waveform generator generates an analog voltage waveform from a digital form of an arc's captured voltage waveform. A current waveform generator generates an analog current waveform from a digital form of an arc's captured current waveform. The analog voltage and current waveforms are sequenced in time to synthesize the arcing condition created by the arc's current and voltage waveforms.
Another embodiment of the invention comprises a system for arc detection testing using synthesized arcs. This system uses similar voltage and current waveform generators to generate an arc's analog form voltage and current waveform from a digital form of the arc's captured waveforms. The voltage and current waveforms are also sequenced in time. A voltage waveform amplifier is included with the output of the voltage waveform generator connected in circuit with the input of said voltage waveform amplifier. A current waveform amplifier is also included, the output of the current waveform generator connected in circuit with the input of the current waveform amplifier. The output of voltage and current waveform amplifiers connected in circuit to a device under test to test its response to the waveforms.
A method for testing a device's response to a simulated arcing condition is also disclosed. An electric arc's voltage and current waveforms are captured in digital form. An analog form voltage and current waveform is generated from said captured digital voltage and current waveforms. The analog form voltage and current waveforms are applied to a device under test and the device is monitored to determine its response to the analog waveforms.
The invention has many advantages over prior arc syntheses testing systems and methods. The invention allows for manipulation of the arc waveform to simulate different signal propagations and system impedances. The invention can combine different waveforms to use load signatures in combination with arc signatures to prove no false trips.
The invention can also validate brown-out conditions and operating characteristics. It can also simulate proximity of the device under test to the arcing condition, which can changes the characteristics of the signal experienced by the device under test. The new tester allows countless permutations of conditions to be more efficiently simulated by programming them into the simulated waveforms. The invention also allows for arc testing of the device at different frequencies.
These and other features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of preferred embodiments, taken together with the accompanying drawings, in which:


REFERENCES:
patent: 5729145 (1998-03-01), Blades
patent: 6191589 (2001-02-01), Clunn
patent: 6426632 (2002-07-01), Clunn
patent: 2571888 (1986-04-01), None
Patent Abstracts of Japan, vol. 1997, No. 10, Oct. 31, 1997

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