Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2002-11-07
2004-11-09
Zarroli, Michael C. (Department: 2839)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S067000, C439S068000
Reexamination Certificate
active
06814584
ABSTRACT:
FIELD OF THE INVENTION
This invention is generally directed to an electrical connector which provides electrical interconnection between two conductive elements. More particularly, the invention contemplates a connector that includes an array of electrical pathways set within a silicone body which uses spring force to provide excellent electrical connection between two conductive elements, such as a silicon die and a circuit board.
BACKGROUND OF THE INVENTION
The interconnection of a silicon die or other electronic devices to circuit boards has typically been done by wire bonding between conductive pads on the silicon die and metal leads which are ultimately soldered onto the circuit board. The metal leads provide input/output connections between the silicon die and the circuit board. The trend is to package more devices in a given area on the circuit board which results in the need for higher lead counts. An increase in lead count has been achieved by making the pitch of the leads smaller and by increasing the number of sides or surfaces from which the leads extend. The limitation of this technique is reached, however, when it is no longer possible to stamp smaller metal lead frames. The result is the need for more input/output connections per die area, higher power densities (i.e. heat) and the need for better packaging techniques.
Examples of such interconnections currently used include the Ball Grid Array (BGA), the CIN::APSE connector produced by Cinch Connector, the Wire on Wafer (WOW) technology developed by Form Factor, Elastomeric Connectors for Electronic Packaging and Testing (U.S. Pat. No. 4,932,883), and the Metalized Particle Interconnect process used by Thomas and Betts.
The BGA was developed to package silicon die onto circuit board substrates with more input/output connections than was possible with metal leaded packaging, such as Quad Flat Packages. This packaging approach utilizes a “high temperature” solder ball attached to pads on the bottom side of the silicon die. By utilizing the entire bottom surface of the die, rather than the perimeter of the die, the number of contacts to the circuit board can be significantly increased when compared to a Quad Flat Pack. This approach requires a substrate such as FR4 or ceramic with plated through holes between the top wire bond pads and the bump pads on the bottom. The bump pads on the bottom have high temperature solder balls mounted to them and then the completed assembly is mounted to the circuit board. This packaging approach is relatively expensive ($0.015 to $0.05 per input/output connection) and does not lend itself to doing wafer level testing in that the die must be packaged prior to burn in testing. The cost of a typical seventy position package is between $1.00 and $3.00.
The second interconnect method, CIN::APSE is primarily used to interconnect high end silicon devices to circuit boards. It includes a flat plastic frame with a grid pattern of holes with a pitch between 0.8 mm and 2 mm into which a piece of gold plated “steel wool” is pressed. This assembly is compressed between the two conductive pads providing electrical contact between them. A typical hold-down force for this connector is two ounces per contact and can result in several hundred pounds of total hold down force. The cost of CIN::APSE connectors averages $0.04 per contact. Thus, the cost of a typical seventy position device is $2.80. This approach to electrical component packaging is relatively expensive and does not lend itself to wafer level testing.
A third technology, Wire On Wafer (WOW), relies on the mounting of metal springs directly onto the silicon die. These springs provide an electrical interconnection between the die and the mating surface such as a circuit board. Its advantages include relatively low cost and the ability to do wafer level testing. The disadvantages include the fact that the memory manufacturers will need to install large amounts of equipment to manufacture and mount the springs onto the die. The viability and cost effectiveness of this packaging approach has not yet been determined.
A fourth approach to silicon packaging relies on using an elastomeric substrate that is selectively metalized on the surface. Through holes are used to electrically connect the bottom pads to the upper pads. The metalized pads on the flat elastomeric surface are offset from the plated through hole such that when then the elastomer is compressed it will not break the electrical connector within the barrel of the plated through hole. An example of this type of connector is described in U.S. Pat. Nos. 5,071,359 and 5,245,751.
The present invention provides an electrical connector which overcomes the problems presented in the prior art and which provides additional advantages over the prior art. Such advantages will become clear upon a reading of the attached specification in combination with a study of the drawings.
OBJECTS AND SUMMARY OF THE INVENTION
A general object of the present invention is to provide an electrical connector which eliminates the need for wire bonding metal leads.
An object of the present invention is to provide an electrical connector which provides more input/output connections per area on the circuit board than is capable with some prior art packaging techniques.
A further object of the present invention is to provide an electrical connector which enables electrical contact between the connector and conductive pads on a circuit board, a silicon die or other electronic device.
Another object of the present invention is to provide an electrical connector which can be manufactured cost effectively.
A specific object of the present invention is to provide an electrical connector which allows for wafer level testing.
Briefly, and in accordance with the foregoing, the present invention discloses an electrical connector which eliminates the need for metal lead frames, provides a greater number of input/output connections per area on the circuit board, provides excellent electrical connection between the devices to be connected, allows for wafer level testing for an entire array of completed integrated chips, and can be cost effectively manufactured. The electrical connector includes an elastomeric base which is formed with through holes and raised elastomeric bumps. The through holes and bumps are metalized to provide an electrical path between the devices to be connected such as a silicon die and the circuit board. The raised bumps are provided on the top and bottom surfaces of the elastomeric base, and through the use of compressive forces enable electrical contact between the conductive pads on the electrical devices and the plated holes. The raised bumps provide spring force to create a good electrical contact, as well as compliance between the devices being interconnected.
Examples of areas of use include surface mount connector mounting, display device interconnection as used for example in liquid crystal displays (LCDs), as well as interconnection of various silicon devices.
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Molex Incorporated
Zeitler Robert J.
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