Elasticity buffer for data/clock synchronization

Details Elasticity buffer for data/clock synchronization Elasticity buffer for data/clock synchronization

1992-02-21

1994-06-21

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

370102, 365221, 365233, 365240, 377 50, H04L 700

Patent

active

053234260

ABSTRACT:
An elasticity buffer for use in a data transmission system having a transmitter and a receiver and utilizing a data transfer protocol that periodically supplies an elasticity element that can be deleted or replicated by the elasticity buffer to maintain the synchronous transfer of data elements. The elasticity buffer includes: a memory array and at least one flag per memory location operative to be set to a first or second state; a write controller operating at the transmitter clock for writing the data elements into the memory locations in a sequential order and setting the corresponding flags; a read controller operating at the receiver clock for reading the data elements from the memory locations in the sequential order; and a flag controller for reading the flags, determining if the transmitter clock is faster or slower than the receiver clock from the pattern of flags read from memory, communicating a delete signal to the read controller to delete an elastic symbol if the transmitter clock leads the receiver clock, and communicating a replicate signal to the read controller if the transmitter clock lags the receiver.

REFERENCES:
patent: 4811340 (1989-03-01), McEachern et al.
patent: 4920547 (1990-04-01), Murakami
patent: 4996698 (1991-02-01), Nelson
SCI, Scalable, Coherent Interface: Logical, Physical and Cache Coherence Specification, P1596/D2.00 Nov. 18, 1991, Draft, IEEE Standards Department, Piscataway, New Jersey, pp. 2-28 and 87-90.

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