Elastic self-timed interface for data flow elements embodied as

Details Elastic self-timed interface for data flow elements embodied as Elastic self-timed interface for data flow elements embodied as

1996-10-24

1999-10-12

Powell, Mark R.

Electrical computers and digital processing systems: processing

Architecture based instruction processing

712 23, 712 25, 712218, 712232, 708521, G06F 900, G06F 104

Patent

active

059648660

ABSTRACT:
The invention relates to a processor having a data flow unit for processing data in a plurality of steps. In one version, the data flow unit includes a plurality of consecutive stages which include logic for performing steps of the data processing, the stages being coupled together by a data path, at least one stage being coupled to a transceiver which causes data to be provided to the stage for processing or to bypass the stage unprocessed in response to a stage enable signal; a synchronizer which receives processed data from the stages and causes the processed data to be provided to external logic in synchronization with a clock signal.

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