1997-03-10
1998-11-17
An, Meng-Ai T.
395310, 395840, 395878, 395559, G06F 938
Patent
active
058389369
ABSTRACT:
An elastic bus interface receives and registers an external data transfer signal and generates an internal data transfer signal that always begins at the beginning of the subsequent clock cycle regardless of the time of arrival of the external data transfer signal. By employing a plurality of data output registers in a pipeline and using only the internal data transfer signal, data is fed to a bus so as to ensure that almost a complete clock cycle is available for setup time to accomplish data transfer. The invention can operate with high speed buses using only simple conventional circuitry and modest process geometries requiring only minimal chip area and power.
REFERENCES:
patent: 5157772 (1992-10-01), Watanabe
patent: 5619668 (1997-04-01), Zaidi
Chau Vi
Su Sam
Tarr Dan
An Meng-Ai T.
Dharia Rupal D.
Emulex Corporation
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