Elastic buffers for serdes word alignment and rate matching...

Details Elastic buffers for serdes word alignment and rate matching... Elastic buffers for serdes word alignment and rate matching...

2000-04-28

2004-02-17

Ton, Dang (Department: 2661)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S366000, C370S504000, C375S372000

Reexamination Certificate

active

06693918

ABSTRACT:

BACKGROUND OF THE INVENTION
Consider a high speed stream of data from a source environment, say, a fiber optic link having a bit data rate of 12.5 GHz, where this data is to be delivered to a destination environment and then processed some way in real time at that rate. One way that is done is to apply the high speed data stream to a Serializer/Deserializer (SERDES) that separates the data into, say, four adjacent streams often bit parallel data at a word rate of 312.5 MHZ. At the time of their origination the four data streams (hereinafter referred to as lanes) are in synchronous alignment, having all been created in a single common environment according to a common clock signal. It is thus the lanes of parallel data that are sent from the source environment (the SERDES) to some destination environment (perhaps a Media Access Controller, or MAC). Variations in the effective length of a lane or of its propagation constant can cause words that were sent into their respective lanes at the same time to emerge therefrom at different times. This problem is called word alignment. Misaligned words must eventually be correctly realigned, or else the reconstructed data will be corrupt. Prior art techniques for performing word alignment have involved the use of high speed clocks and techniques for “stretching” and “compressing” the electrical waveforms for the words. That is truly an ugly business fraught with many difficulties, such as the phase locking of very high speed clocks, and a servo system having some rather complicated logic.
It would be desirable if there were a simple and reliable way to perform word alignment that did not involve the use of high speed clocks and the distorted reconstruction of an electrical waveform for a word of data.
Another problem that besets the SERDES/MAC environment described above is that of rate matching. To appreciate this problem, note that the words are stored in First In First Out register structures (FIFO's). In the prior art the words are aligned before being stored; where they are stored in a FIFO is determined by a Write Pointer (WP). Each of the four lanes of data (annotated individually with the suffixes “_
0
” through “_
3
”) has its own FIFO, so the collection of FIFO's is FIFO_
1
through FIFO_
3
and their respective Word Pointers are WP_
0
through WP_
3
. The individual WP_i are created from circular counters that are incremented by individual lane clocks that are recovered from self clocking data in the respective lanes. There is a collection of Read Pointers (RP_i) that correspond to the WP_i, and they originate from a circular counter driven by a clock in the destination environment. There is no mechanism provided to force the WP_i and RP_i to increment at exactly the same rate; they are allowed to be slightly different, owing to drift, tolerances, etc. This was a decision made at the system design level, and is enforced by various written standards from standard setting agencies. As a consequence, there needs to be a way to prevent data corruption when one of the Read or Write Pointers begins to overtake the other. The various standard protocols for such systems as we have been discussing (involving Ethernet, HARI, and FIBRE, etc.) provide a mechanism for rate matching, so that the source environment and destination environment clocks need not run at exactly the same rate. The principal element of these mechanisms is the existence of Inter-Packet Gaps (IPG's) that contain special idle characters (“K” and “R”) that are guaranteed never to occur in the data proper. (This bit of magic does not impose on the data sent the limitation that it avoid certain bit patterns. It involves instead an expansion of the number of bits used to express the data, so that there are unused codes in the expanded version. K and R belong to these unused codes in the expanded coding. The legend “8B10B” is the designation of one such expansion scheme developed by IBM, where eight bit bytes are re-encoded as ten bit bytes.) Since K and R never appear in the actual data, their presence indicates the occurrence of an IPG, and thus allows the high speed detection in real time of an IPG. The various protocol standards do not specify any particular size for an IPG, except that it be at least of a certain minimal size. Furthermore, the size of an IPG may be adjusted during transmission. Thus, effective data rate matching is achieved by adding or deleting K and R characters to the IPG's for all lanes whenever the Read and Write Pointers for any one lane get too close together. Now, and this is a neat trick, the IPG's to be modified exist as sequences of idle characters in the FIFO's. The ususal way to do rate matching is periodically to simply bump a Read Pointer ahead to delete a character or to bump it back to insert a character by repeating it. The character streams transmitted by such reading of the content of the FIFO looks exactly like deleting or inserting characters, respectively, even though no characters in the FIFO's actually change. This adjusting (as needed) of the effective size of the IPG's allows the real data to be sent at (continually) slightly mismatched rates without corruption. This is an established mechanism, and it would be especially desirable if it could be left intact, or even better, if it could cooperate with an improved way of performing word alignment, so that one mechanism does double duty, as it were.
SUMMARY OF THE INVENTION
A solution to the word alignment problem described above is to have for each lane: a recovered clock, a Write Pointer counter and a FIFO. Misaligned words are simply stored in their FIFO's according to the respective recovered clocks and straightforward increments of the various Write Pointers WP_i. One of the lanes is selected as a reference, and the contents of the other FIFO's are inspected to determine the nature of their misalignment, if any. Then the values from the Read Pointer counters RP_i are individually offset by corresponding amounts to compensate for the misalignment, so that when data is read it is indeed aligned. These offsets by corresponding amounts are simply individual per lane adjustments to the various Read Pointers, and cooperate with the adjustments to those Read Pointer for rate matching.


REFERENCES:
patent: 6594329 (2003-07-01), Susnow

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