Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-09-27
2004-03-09
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S036000, C345S045000, C313S463000, C313S518000, C315S169300
Reexamination Certificate
active
06703992
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrolumnescence display device comprising electroluminescence elements and thin film transistors.
2. Description of Prior Art
In recent years, electroluminescence (referred to herein after as “EL”) display devices comprising EL elements have gained attention as potential replacements for CRTs and LCDs. Research has been directed to the development of EL display devices using, for example, thin film transistors (referred to hereinafter as “TFT”) as switching elements to drive the EL elements.
FIG. 1A
is a plan view showing a display pixel of an organic EL display device.
FIG. 1B
shows a cross-sectional view taken along line A—A of
FIG. 1A
while
FIG. 1C
shows a cross-sectional view taken along line B—B of FIG.
1
A.
As shown in these drawings, a display pixel
20
is formed in a region surrounded by a gate line GL and a data line DL. A first TFT serving as a switching element is disposed near an intersection of those lines. The source of the TFT
1
simultaneously functions as a second capacitor electrode
3
such that, together with a first capacitor electrode
2
, it forms a capacitor
8
. The source is connected to a gate electrode
15
of a second TFT
4
that drives the organic EL element. The source of the second TFT
4
contacts with an anode
6
of the organic EL element, while the drain of the TFT
4
is connected to a power source line (power source line) VL.
The first capacitor electrode
2
, which is made of a material such as chromium, overlaps, over a gate insulating film
7
, the second capacitor electrode
3
integral with the source of the first TFT
1
. The first capacitor electrode
2
and the second capacitor electrode
3
together store charges with the gate insulating film
7
being interposed therebetween as a dielectric layer. The storage capacitors
8
serves to retain voltage applied to the gate electrodes
15
of the second TFT
4
.
The first TFT
1
, the switching TFT, will now be described.
First gate electrodes
11
made of refractory metal such as chromium (Cr) or molybdenum (Mo) are formed on a transparent insulator substrate
10
made of quartz glass, non-alkali glass, or a similar material. As shown in
FIG. 1A
, the first gate electrodes
11
are integrally formed with the gate line GL such that a plurality of these electrodes extend from the gate line GL in the vertical direction in parallel with each other.
Referring to
FIG. 1B
, the first capacitor electrode
2
formed in the same process as that of the first gate electrodes
11
is provided to the right side of the first gate electrodes
11
. This first capacitor electrode
2
, which constitutes the storage capacitor
8
, has an enlarged portion between the first TFT
1
and the second TFT
4
as shown in FIG.
1
A and is integral with a storage capacitor line CL extending therefrom in the directions.
A first active layer
12
composed of poly-silicon (referred to hereinafer as “p-Si”) film is formed on the gate insulating film
7
. The first active layer
12
is of a so-called LDD (Lightly Doped Drain) structure. Specifically, low-concentration regions are formed on both sides of the gate.
Source and drain regions, which are high-concentration regions, are further disposed on the outboard sides of the low-concentration regions. On the first active layer
12
, a stopper insulating film
13
made of Si oxidation film is formed so as to prevent ions from entering the first active layer
12
.
An interlayer insulating film
14
formed by sequential lamination of a SiO
2
film, a SiN film, and a SiO
2
film is provided on the entire surface over the gate insulating film
7
, the active layer
12
, and the stopper insulating film
13
. The data line DL which functions as a drain electrode is electrically connected, through a contact hole C
1
formed in the interlayer insulating film
14
, to the drain in the active layer
12
. A planarizing insulating film
18
made, for example, of an insulating organic resin is also formed over the entire surface for planarization.
In EL display devices which are driven by an electric current, the EL layers must have a uniform thickness.
Otherwise, current concentration may occur in a portion of the layer having thinner thickness. Thus, a significantly high level of planarity is required at least in portions where the EL elements are to be formed, and therefore the above-described planarizing film
18
made of a material having fluidity prior to hardening is employed.
The second TFT
4
which drives the organic EL element will be described with reference to
FIGS. 1A and 1C
.
On the insulating substrate
10
, second gate electrodes
15
made of the same material as the first gate electrodes
11
are provided, and a second active layer
16
is further formed on the gate insulating film
7
. Then, a stopper insulating film
17
is formed on the second active layer
16
in a manner similar to the above-mentioned stopper insulating film
13
.
Intrinsic or substantially intrinsic channels are formed in the second active layer
16
above the gate electrodes
15
, and source and drain regions are formed on respective sides of these channels by doping p-type impurities, thereby constituting a p-type channel TFT.
The above-described interlayer insulating film
14
is provided on the entire surface over the gate insulating film
7
and the second active layer
16
, and the power source line VL is electrically connected, through a contact hole C
2
formed in the interlayer insulating film
14
, to the drain in the active layer
16
. Further, the planarizing film
18
is formed over the entire surface, such that the source is exposed through a contact hole C
3
formed in the planarizing film
18
and the interlayer insulating film
14
. A transparent electrode made of ITO (Indium Tin Oxide) that contacts the source through this contact hole C
3
, namely, the anode
6
of the organic EL element
20
, is formed on the planarizing insulating film
18
.
The organic EL element
20
is formed by laminating, in order, the anode
6
, an emissive element layer EM comprising a first hole transport layer
21
, a second hole transport layer
22
, an emissive layer
23
and an electron transport layer
24
, and a cathode
25
made of a magnesium-indium alloy. The cathode
25
is substantially disposed over the entire surface of the organic EL elements.
The principle and operation for light emission of the organic EL element is as follows. Holes injected from the anode
6
and electrons injected from the cathode
25
recombine in the emissive layer
23
, to thereby excite organic molecules constituting the emissive layer
23
, thereby generating excitons. Through the process in which these excitons undergo radiation until deactivation, light is emitted from the emissive layer. This light radiates outward through the transparent anode via the transparent insulator substrate and resultant light emission is observed.
In this way, electric charge corresponding to the display data and applied via the source S of the first TFT
1
is accumulated in the storage capacitor
8
and applied to the gate electrodes
15
of the second TFT
4
. According to this voltage, a current is applied to the organic EL element via the second TFT
4
and the organic EL element emits light by the light emitting principle as described above.
Active research of the above-described EL elements is expected continue, and EL display devices with a high yield rate are required. Further, to achieve high resolution, the size of a display pixel must be minimized so that a maximum number of display pixels can be efficiently fabricated into a display pixel region having a limited size.
In the current art, when a specific attention is drawn to one display pixel region as shown in
FIG. 1A
, a significant number of points where the conductive layers intersect are observed. Specifically, each display pixel includes four intersections, namely, an intersection between the gate line GL and the data line DL, an intersection between
Bella Matthew C.
Cantor & Colburn LLP
Sanyo Electric Co,. Ltd.
Tran Tam
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