EFM signal frame period detecting circuit, and system for contro

Details EFM signal frame period detecting circuit, and system for contro EFM signal frame period detecting circuit, and system for contro

1998-06-22

2000-09-12

Wamsley, Patrick

Coded data generation or conversion

Digital code to digital code converters

Data rate conversion

369 47, H03M 700, H04L 700, G11B 1552

Patent

active

061183938

ABSTRACT:
A system for controlling the frequency of a bit synchronizing clock signal used for reproducing an EFM signal, comprises an EFM signal frame period detecting circuit for frequency-dividing an EFM signal by 117 to output a 1/117 frequency-divided signal as a frame period signal. A control unit counts the level transition interval of the EFM signal by the bit synchronizing clock signal, selects a maximum count value in a detecting duration defined by each frame period signal, and compares the maximum count value with a predetermined value corresponding to the bit length of a frame synchronizing signal included in the EFM signal. When the maximum count value is larger than the predetermined value, the control unit controls to decrease the oscillation frequency of a bit synchronizing clock signal generating circuit, and when the maximum count value is larger than the predetermined value, the control unit controls to increase the oscillation frequency of a bit synchronizing clock signal generating circuit, with the result that the frequency of the bit synchronizing clock signal is controlled to maintain the counted pulse width of the frame synchronizing signal equal to the length of 11 bit synchronizing clock signals.

REFERENCES:
patent: 4472686 (1984-09-01), Nishimura et al.
patent: 4532561 (1985-07-01), Kimura et al.
patent: 4901300 (1990-02-01), Van Der Zande et al.
patent: 5187699 (1993-02-01), Raaymakers et al.

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