Coded data generation or conversion – Digital code to digital code converters – To or from minimum d.c. level codes
Patent
1996-02-22
2000-02-08
Gaffin, Jeffrey A.
Coded data generation or conversion
Digital code to digital code converters
To or from minimum d.c. level codes
341 59, G06F 500, G11B 700
Patent
active
06023234&
ABSTRACT:
There is provided an EFM encoder comprising a DSV calculator which is smaller in circuit scale than a conventional DSV calculator. The above DSV calculator has a merging-bit DSV calculator, a frame-signal DSV/polarity evaluator, adding means, and an overflow/underflow processor. The merging-bit DSV calculator calculates merging-bit DSV data based on merging bits and on a cumulative polarity signal. The frame-signal DSV/polarity evaluator outputs frame-signal DSV data in consideration of the polarity in the final bit of the merging bits. The adding means adds up the cumulative DSV data, the merging-bit DSV data, and the frame-signal DSV data so as to calculate DSV. The overflow/underflow processor performs, when overflow or underflow has occurred in the result of calculation from the adding means, exception handling with respect to the calculation result and outputs the calculation result that has undergone the exception handling as new cumulative DSV data. Even when overflow or underflow has occurred in the obtained cumulative DSV data, the accuracy of DSV calculation performed by the DSV calculator is not reduced.
REFERENCES:
patent: 5077721 (1991-12-01), Sako et al.
patent: 5349349 (1994-09-01), Shimizume
patent: 5375249 (1994-12-01), Cho
patent: 5438621 (1995-08-01), Hornak eta l.
Gaffin Jeffrey A.
Jean-Pierre Peguy
Matsushita Electric - Industrial Co., Ltd.
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