Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-01-08
2008-01-08
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185210, C365S185190
Reexamination Certificate
active
11550502
ABSTRACT:
A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
REFERENCES:
patent: 5220531 (1993-06-01), Blyth
patent: 5313421 (1994-05-01), Guterman
patent: 5412601 (1995-05-01), Sawada
patent: 5521865 (1996-05-01), Ohuchi
patent: 5570315 (1996-10-01), Tanaka
patent: 5652719 (1997-07-01), Tanaka
patent: 5712180 (1998-01-01), Guterman
patent: 5712815 (1998-01-01), Bill
patent: 5761222 (1998-06-01), Baldi
patent: 5870344 (1999-02-01), Ozawa
patent: 5880993 (1999-03-01), Kramer et al.
patent: 5926409 (1999-07-01), Engh
patent: 5949714 (1999-09-01), Hemink
patent: 5969986 (1999-10-01), Wong
patent: 6151248 (2000-11-01), Harari
patent: 6222762 (2001-04-01), Guterman
patent: 6243290 (2001-06-01), Kurata
patent: 6266270 (2001-07-01), Nobukata
patent: 6278634 (2001-08-01), Ra
patent: 6301161 (2001-10-01), Holzmann
patent: 6317364 (2001-11-01), Guterman
patent: 6392931 (2002-05-01), Pasotti et al.
patent: 6424566 (2002-07-01), Parker
patent: 6522580 (2003-02-01), Chen
patent: 6525964 (2003-02-01), Tanaka
patent: 6529412 (2003-03-01), Chen
patent: 6532172 (2003-03-01), Harari
patent: 6643188 (2003-11-01), Tanaka et al.
patent: 6788579 (2004-09-01), Gregori et al.
patent: 7002843 (2006-02-01), Guterman et al.
patent: 7139198 (2006-11-01), Guterman et al.
patent: 2002/0024846 (2002-02-01), Kawahara
patent: 2002/0057598 (2002-05-01), Sakamoto
patent: 2002/0118574 (2002-08-01), Gongwer
patent: 2003/0147278 (2003-08-01), Tanaka
patent: 1249842 (2002-10-01), None
Kurata, Hideaki, et al., Constant-Charge-Injection Programming for 10-MB/s Multilevel AG-AND Flash Memories, 2002 Symposium On VLSI Circuits Digest of Technical Papers, pp. 302-303 (copy not submitted because it was submitted in prior U.S. Appl. No. 10/766,271, filed Jan. 27, 2004).
Johnson, William S., et al., Session XII: ROMs, PROMs, and EROMS, 1980 IEEE International Solid State Circuits Conference, pp. 152-153 (copy not submitted because it was submitted in prior U.S. Appl. No. 10/766,271, filed Jan. 27, 2004).
Nobukata, Hiromi, et al., A 144Mb 8-Level NAND Flash Memory with Optimized Pulse Width Programming, 1999 Symposium on VLSI Circuits Digest of Technical Papers, pp. 39-40 (copy not submitted because it was submitted in prior U.S. Appl. No. 10/766,271, filed Jan. 27, 2004).
Ohkawa, Masayoshi, et al., TP 2.3: A 98 mm2 3.3V 64Mb Flash Memory with FN-NOR Type 4-level Cell, 1996 IEEE International Solid-State Circuits Conference, pp. 36-37 (copy not submitted because it was submitted in prior U.S. Appl. No. 10/766,271, filed Jan. 27, 2004).
Office Action, dated Aug. 27, 2007, U.S. Appl. No. 11/550,499, filed Oct. 18, 2006.
Fong Yupin
Guterman Daniel C.
Mokhlesi Nima
Hur J. H.
Sandisk Corporation
Vierra Magen Marcus & DeNiro LLP
LandOfFree
Efficient verification for coarse/fine programming of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Efficient verification for coarse/fine programming of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient verification for coarse/fine programming of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3928401