Efficient variable length encoder and decoder

Details Efficient variable length encoder and decoder Efficient variable length encoder and decoder

1996-12-17

1998-12-15

Lee, Richard

Television

Bandwidth reduction system

Data rate reduction

3488451, 3488452, H04N 724

Patent

active

058502610

ABSTRACT:
There are provided an encoding circuit 2 which encodes pixel data by an ADRC method; a dividing circuit 3 which divides the data from the encoding circuit 2 into a plurality of bit planes; an encoding circuit 4 which encodes, with run length coding and Huffman coding, the data at every bit plane of the plurality of bit planes divided and generated by the dividing circuit; and a framing circuit 5 which adds an error correcting code to the encoded pixel data. The data encoded by the ADRC method are divided into the bit plane for each of MSB, 2nd MSB, . . . LSB and the respective bit planes are processed by the run length coding and Huffman coding, so that it is possible to compress the data with a high compressibility and at the same time minimize the lowering of the restoration capability of the data when an error is generated.

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Patent Abstracts of Japan, vol. 16, No. 221 (E-1205) 22 May 1992, JP-A-04 037 367 (Fujitsu General Limited) 7 Feb. 1992.

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