Efficient use of the base register auto-increment feature of mem

Data processing: software development – installation – and managem – Software program development tool – Translation of code

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717 5, G06F 1204

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active

061517054

ABSTRACT:
The present invention is a compiler optimization algorithm that reduces address computation overhead for architectures that support an auto-increment addressing mode for memory access instructions. The compiler algorithm identifies opportunities for auto-increment synthesis in a low level intermediate representation. Candidate loads and stores are transformed to use a base+displacement addressing mode (even if a base+displacement addressing mode is not supported in the target architecture) prior to instruction scheduling. After instruction scheduling, the pseudo (base+displacement) instructions are transformed back into memory operations that increment their base register operands to set up effective memory addresses.

REFERENCES:
patent: 5167026 (1992-11-01), Murray et al.
patent: 5475856 (1995-12-01), Kogge
patent: 5699544 (1997-12-01), Robbins et al.
patent: 5860130 (1999-01-01), Yamanaka et al.
Greenberg. IBM Offers Sneak Peek at RISC Work--Some Details On Chip Emerge At IEEE Technical Symposium. Unix Today. n 034, 32, Nov. 1989.
C.B. Hall, et al., Performance Characteristics of Architectural Features of the IBM RISC System/600, 1991 ACM 0-89791-380-9/91/0003-0303, pp. 303-309.
Vatsa Santhanam, Register Reassociation in PA-RISC Compilers, Jun. 1992 Hewlett-Packard Journal, pp. 33-38.
Peter Markstein, et al., Chapter 9, Strength Reduction, Dec. 28, 1992, from Optimization in Compilers, ACM press, pp. 1-40, & 101-102.
Kevin Harris, et al., Chapter 16, VAX Fortran, Dec. 28, 1992, from from Optimization in Compilers, ACM press, pp. 1-43, & 101-102.
Richard L. Sites, Compilation of Loop Induction Expressions, 1977, vol. 1, ACM Transactions on Programming Languages & Systems, pp. 50-57.
Kevin O'Brien, et al., Advanced Compiler Technology for the RISC System/6000 Architecture, 1990, IBM RISC System/6000 Technology, pp. 154-161.

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