Efficient two-stage digital-to-analog converter using...

Details Efficient two-stage digital-to-analog converter using... Efficient two-stage digital-to-analog converter using...

1998-12-30

2001-02-20

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S144000

Reexamination Certificate

active

06191720

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to data converters. In particular, the invention relates to digital-to-analog converters (DAC's).
2. Description of Related Art
A digital-to-analog converter (DAC) usually includes a resistor network and an array of switches or multiplexer circuit. The N-bit digital input is applied to the multiplexer circuit to control the switches. The size of the array of switches is a function of the number of input bits N. A large value of N may result in a prohibitively large array size. To reduce the complexity of the switch array, many DAC's utilize a multi stage switching scheme.
FIG. 1
illustrates a prior art 2-stage DAC. The prior art DAC
100
includes a first resistor network
110
, a first stage multiplexer circuit
120
, a second resistor network
130
, and a second stage multiplexer circuit
140
. The N-bit digital input is composed of J most significant bits (MSB's) and K least significant bits (LSB's).
The first resistor network
110
includes a series of resistors R
1,0
, R
1,1
, . . . R
1,2
J
whose values are selected to provide 2
J
voltage values. The first stage multiplexer circuit
120
selects one out of the 2
J
voltage values as provided by the first resistor network
110
. The multiplexer circuit
120
is controlled by the J most significant bits (MSB's) of the N-bit input. The second resistor network
130
divides the voltage output of the first stage multiplexer circuit
120
into further 2
K
voltage values. The second stage multiplexer circuit
140
selects one out of the 2
K
voltage values to produce the final output voltage. The second stage multiplexer circuit
140
is controlled by the K least significant bits (LSB's) of the N-bit input.
To reduce the well understood “loading effect” of the second resistor network, a high unit resistance ratio between the second and the first resistor networks is required, which tends to increase the size of the converter and significantly impact the speed performance. There has been design which inserts two unit gain buffers in between the first and the second resistor networks. This method reduces the loading effect, but does not solve problems caused by the offset of the buffers.
Although the 2-stage DAC reduces the hardware complexity from the single stage DAC, the amount of hardware is still high. There are two resistor networks and two multiplexer circuits. For medium to high resolution DACs, it is desirable to reduce the hardware complexity further.
Therefore there is a need in the technology to provide a simple and efficient technique to reduce the hardware complexity in DAC.
SUMMARY
The present invention is a method and apparatus for converting a digital word into an analog quantity. A first plurality of signals is generated from a resistor network. A first signal is selected from the first plurality of signals based on a first half of the digital word. A second plurality of signals is generated from the resistor network using the selected first signal. A second signal is selected from the second plurality of signals based on a second half of the digital word. The second signal corresponds to the analog quantity.
In one embodiment, the digital-to-analog converter includes a resistor network, an input multiplexer, a selector, and top and bottom sample-and-hold circuits. The resistor network generates a first plurality of signals. The input multiplexer receives the digital word to provide a first half and a second half of the digital word. The selector is coupled to the resistor network to select first top and bottom signals from the first plurality of signals based on the first half of the digital word. The top and bottom sample-and-hold circuits are coupled to the selector to provide top and bottom feedback signals from the selected first top and bottom signals to the resistor network. The resistor network generates a second plurality of signals. The selector selects second top and bottom signals from the second plurality of signals based on the second half of the digital word. One of the second top and bottom signals corresponds to the analog quantity.


REFERENCES:
patent: 4099173 (1978-07-01), Zeskind et al.
patent: 4973979 (1990-11-01), Ikeda
patent: 5252975 (1993-10-01), Yuasa et al.
patent: 5703588 (1997-12-01), Rivoir et al.

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