Efficient transistor-level circuit simulation

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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C703S002000, C703S015000, C716S030000, C716S030000

Reexamination Certificate

active

07555416

ABSTRACT:
Techniques are described for performing analysis of circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.

REFERENCES:
patent: 5313398 (1994-05-01), Rohrer et al.
patent: 5379231 (1995-01-01), Pillage et al.
patent: 5467291 (1995-11-01), Fan et al.
patent: 5694052 (1997-12-01), Sawai et al.
patent: 5790415 (1998-08-01), Pullela et al.
patent: 5888875 (1999-03-01), Lasky
patent: 6141676 (2000-10-01), Ramirez-Angulo et al.
patent: 6308300 (2001-10-01), Bushnell et al.
patent: 6557148 (2003-04-01), Nishida et al.
patent: 6577992 (2003-06-01), Tcherniaev et al.
patent: 6662149 (2003-12-01), Devgan et al.
patent: 6665849 (2003-12-01), Meuris et al.
patent: 2002/0131135 (2002-09-01), Chow et al.
patent: 2003/0065965 (2003-04-01), Korobkov
patent: 2003/0075765 (2003-04-01), Ohnakado et al.
patent: 2003/0200071 (2003-10-01), Zhang et al.
patent: 2003/0204828 (2003-10-01), Iwanishi
patent: 2004/0008096 (2004-01-01), Liu et al.
patent: 2004/0044510 (2004-03-01), Zolotov et al.
patent: 2005/0076318 (2005-04-01), Croix et al.
patent: 2005/0096888 (2005-05-01), Ismail
patent: 2005/0102124 (2005-05-01), Root et al.
patent: WO 2004/109452 (2004-12-01), None
patent: WO 2007/005005 (2007-01-01), None
Beattie, M., et al., “IC Analyses Including Extracted Inductance Models” Proceeding of the 36thACM/IEEE conference on Design automation. pp. 915-920. Jun. 21-25, 1999 (6 pages). New Orleans, Louisiana.
Chen, T., et al., “Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods,” IEEE/ACM Design Automation Conference, University of Wisconsin-Madison, pp. 559-562, 2001.
David Blaauw, Rajendran Panda, and Rajat Chaudhry, “Design and Analysis of Power Distribution Networks,”Design of high-performance microprocessor circuits, Chapter 24, pp. 499-521, IEEE Press 2001 by the Institute of Electrical and Electronics Engineers, Inc., 3 Park Avenue, 17thFloor, New York, NY.
De Geus, A.J., “SPECS: simulation program for electronic circuits and systems.” In Proceedings of the International Symposium on Circuits and Systems, pp. 534-537, pp. 10-16, 1984. Queen Elizabeth Hotel, Montreal, Canada.
Devgan, A. and Rohrer, R. A., “Adaptively Controlled Explicit Simulation.” IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. CAD-13(6), pp. 746-762. Jun. 1994.
Devgan, A., et al., “How to Efficiently Capture On-Chip Inductance Effect: Introducing a New Circuit Element K,” Proc. ICCAD 2000, pp. 150-155, (Nov. 2000).
Feldmann, P., and Freund, R. W., “Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm,” Proceedings of 32ndDAC, pp. 474-479, 1995. San Francisco, California. ISBN:0-89791-725-1.
Gala, K., et al., On Chip Inductance Modeling and Analysis, DAC, Jun. 2000, pp. 63-68 Inductance Models, DAC, Los Angeles, California.
He, L., et al., An Efficient Inductance Modeling for Onchip Interconnects, CICC, May 1999, pp. 457-460. Town and Country Hotel, San Diego, California.
Kerns, K.J., et al., “Stable and efficient reduction of substrate model networks using congruence transforms,” Proceedings of ICCAD, pp. 207-214, 1995. San Jose, California.
Kozhaya, , J.N., et al., “Multigrid-like Technique for Power Grid Analysis,” Proc. ICCAD 2001, pp. 480-487, San Jose, California.
Lelarasmee, E., et al., “The Waveform relaxation method for the time-domain analysis of large scale integrated circuits.” IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. CAD-1(3), pp. 131-145, Jul. 1982.
Li, Z., and Shi, C. J., SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects, pp. 793-799, ICCAD 2003. San Jose, California.
Lin, S., and E.S. Kuh, “transient simulation of lossy interconnects based on the recursive convolution formulation,” IEEE Transactions on CAS I: Fundamental Theory and Applications, vol. 39, pp. 879-892, Nov. 1992.
Lin, S., et al., “Stepwise equivalent conductance circuit simulation.” IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. CAD-12(5), pp. 672-683, May 1993.
Nassif, S.R., et al., “Fast Power Grid Simulation,” Proceeding of DAC, pp. 156-161, 2000.
Newton, A.R., et al., “Relaxation based electrical simulation.” IEEE Transactions on Computer-Aided Designs of ICs and Systems, vol. CAD-3(4), pp. 308-330, Oct. 1984.
Odabasioglu, A., et al., “PRIMA: Passive Reduced-Order Interconncet Macromodeling Algorithm”, Proc. ACM/IEEE ICCAD Nov. 1997, pp. 58-65, San Jose, California.
Phillips, J.R., et al., “Guaranteed passive balancing transformations for model order reduction,” Proceedings of 39thDAC, pp. 52-57, 2002.
Raghavan, V., et al., “A WESpice: A general tool for the accurate and efficient simulation of interconnect problems,” Proceedings of the 29thACM/IEEE conference on Design automation, pp. 87-92, Jun. 8-12, 1992. Ahaheim, California.
Sakallah, K. A., et al., “SAMSON2: an event driven VLSI circuit simulator.” IEEE Transaction s on Computer-Aided Design of ICs and Systems, vol. 4(4), pp. 668-684, Oct. 1985.
Visweswariah, C., and Rohrer, R. A., “Piecewise Approximate Circuit Simulation.” IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. CAD-10(7), pp. 861-870, Jul. 1991.
White, J., et al., “RELAX2: a new waveform relaxation approach for the analysis of LSI MOS circuits.” In Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 756-759, vol. 2. May 1983, Newport Beach , California.
Zhu, Z. and Cheng, C.K., Power Network Analysis Using and Adaptive Algebraic Multigrid Approach, ACM/IEEE Design Automation Conference, pp. 105-108, Jun. 2003. Anaheim, California.
International Search Report and Written Opinion dated Jun. 2, 2006, for PCT/US05/20369, international filing date Jun. 8, 2005 (9 pages).
Acar et al., “TETA: Transistor Level Waveform Evaluation for Timing Analysis,” IEEE Trans. On Computer-Aided Design, vol. 21, No. 5, (May 2002).
Afshari, E., et al., “Non-Linear Transmission Lines for Pulse Shaping In Silicon,” Proc. of IEEE Custom Integrated Circuits Conference, pp. 91-94, Sep. 2003.
Backhouse et al., “WSix Thin Film for Resistors,” Thin Solid Films, vol. 311, No. 1-2, pp. 299-303 (1997).
Backmann, B.M., et al., “TLC: Transmission Line Caches,” Proceedings of the 36thIEEE International Symposium on Microarchitecture (Micro-36'03), 12 pages (2003).
Black, J.R., “Electromigration Failure Modes in Aluminum Metalization for Semiconductor Devices,” Proc. IEEE, pp. 1587-1594, (2003).
Bobba et al., “IC power distribution challenges,” IEEE/ACM International Conference on Computer Aided Design, pp. 643-650, (2001).
Brandt, A., “A Multi-level adaptive solutions to boundary value problems,” Math. Comput., 31:333-390 (1977).
Cao et al., “HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodeling Engine for RLKC Power Delivery,” IEEE/ACM Design Automation Conference, pp. 379-384, (2002).
Chang et al, “RF/Wireless Interconnect for Inter- and Intra-Chip Communications,” Proceedings of the IEEE, vol. 89, No. 4, pp. 456-466 (2001).
Chang et al., “Near Speed-of-Light Signaling Over On-Chip Electrical Interconnects,” IEEE Journal of Solid-State Circuits, vol. 38, No. 5, pp. 834-838 (2003).
Chen, H., et al., “Interconnect and circuit modeling techniques for full-chip power supply noise analysis,” IEEE Transactions on Components, Packaging, and Manufactured Technology, Part B, vol. 21, No. 3, pp. 209-215, Aug. 1998.
Chen, H., et al., “Surfliner: a distortionless electrical signaling scheme for speed of light on-chip communications,” Proceedings of the 2005 International Conference on Computer Design (ICCD '05), 6 pages, (

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