Efficient TLB entry management for the render operands...

Details Efficient TLB entry management for the render operands... Efficient TLB entry management for the render operands...

2000-01-10

2003-03-25

Vo, Cliff N. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphics processing

Three-dimension

Reexamination Certificate

active

06538650

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microprocessor systems, and more particularly, to translation lookaside buffers for use is conjunction with high performance microprocessors.
2. Art Background
In order to avoid frequent, cycle consuming accesses of main memory, a graphics accelerator system frequently utilizes cache memory. Cache memory is typically comprised of a relatively small amount of static random access memory (SRAM) which is both physically faster than main memory and arranged such that it can be addressed more rapidly than main memory. The graphics accelerator within the system uses the faster cache memory to capture and store information as it is used. The information is stored within the cache memory in accordance with a predetermined mapping policy. Examples of such mapping policies include, direct mapping, set associative making, and fully associative mapping. The storage of information in a cache memory allows the graphics accelerator to quickly and advantageously obtain this information from the cache memory rather than from main memory. The intelligent design and use of a cache memory can substantially enhance the performance of the overall system.
Graphic accelerator systems also typically utilize virtual addressing. Virtual addressing enables the system to effectively create a virtual memory space larger than the actual physical memory space. A graphics accelerator can then advantageously operate in virtual address space using virtual addresses. Frequently, however, these virtual addresses must be translated into physical addresses. One way of accomplishing this translation of virtual addresses into physical addresses is to regularly access translation tables stored in main memory. However, regularly accessing translation tables in main memory tends to slow overall system performance. Accordingly, in order to avoid the need to regularly access translation tables in main memory to accomplish address translation, graphics accelerator systems often use a translation lookaside buffer (TLB) to store or cache recently generated virtual to physical address translations.
A translation lookaside buffer (TLB) can be thought of as a special type of cache memory. As with other types of caches, a TLB is typically comprised of a relatively small amount of memory specially designed to be quickly accessible. A TLB typically incorporates both a tag array and a data array. Within the tag array, each tag line stores a virtual address. This tag line is then associated with a corresponding data line in the data array which stores the physical address translation for the virtual address. Thus, prior to seeking a translation of a virtual address from translation tables in main memory, a graphics accelerator can first refer to the TLB to determine whether the physical address translation of the virtual address is presently stored in the TLB. In the event that the virtual address and corresponding physical address are presently stored is the TLB, the TLB responsively outputs the corresponding physical address, and a time-consuming access of main memory is avoided.


REFERENCES:
patent: 5640533 (1997-06-01), Hays et al.
patent: 5712998 (1998-01-01), Rosen
patent: 6093213 (2000-07-01), Favor et al.
patent: 6362826 (2002-03-01), Doyle et al.

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