Efficient three-dimensional layout method for logic cell arrays

Details Efficient three-dimensional layout method for logic cell arrays Efficient three-dimensional layout method for logic cell arrays

1995-06-07

1998-05-05

Louis-Jacques, Jacques H.

Boots, shoes, and leggings

3958001, 39580011, 36472502, 36472805, G06F 300, G06F 1514

Patent

active

057489424

ABSTRACT:
A method by which a two-dimensional array of logic elements may be interconnected such that they may be modeled as a three-dimensional array, while minimizing routing crossings. The result is an arrangement that is highly efficient for implementation in a silicon die. The preferred model may be extended to a three-dimensional torus where opposing faces of the array are considered to be adjacent. Routing flexibility is increased by increasing local interconnect while minimizing interconnect crossover.

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