Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2005-10-25
2005-10-25
Patel, Paresh (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C340S002280, C340S002290, C379S291000, C379S292000
Reexamination Certificate
active
06958598
ABSTRACT:
A switching topology for communicating signals in an automatic test system includes a plurality of switching circuits each for selectively passing signals or crossing signals. Switching circuits are connected together such that each node of any switching circuit connects to no more than one node of any other switching circuit. This topology offers improved signal integrity, reduced cost, and reduced space as compared with conventional, matrix-style switching topologies.
REFERENCES:
patent: 3435417 (1969-03-01), Haselton, Jr.
patent: 4620304 (1986-10-01), Faran, Jr.
patent: 4635250 (1987-01-01), Georgiou
patent: 4798435 (1989-01-01), Fujiwara et al.
patent: 4837855 (1989-06-01), Hajikano et al.
patent: 5124636 (1992-06-01), Pincus
patent: 5124638 (1992-06-01), Winroth
patent: 5237565 (1993-08-01), Henrion et al.
patent: 5243272 (1993-09-01), Hall
patent: 5371786 (1994-12-01), Paul
patent: 6084873 (2000-07-01), Russell et al.
patent: 6236300 (2001-05-01), Minners
patent: 6594261 (2003-07-01), Boura et al.
patent: 2003/0043015 (2003-03-01), Gershfeld
patent: 2 538 912 (1984-07-01), None
patent: 56117495 (1981-09-01), None
On the bisection width and expansion of butterfly networks Bornstein, C.; Litman, A.; Maggs, B.M.; Sitaraman, R.K.; Yatzkar, T.; Parallel Processing Symposium, 1998. 1998 IPPS/SPDP. Proceedings of the First Merged International . . . and Symposium on Parallel and Distributed Processing 1998 , Mar. 30-Apr. 3, 1998 Page(s): 144-150.
International Search Report.
“Logically Controlled Chip Interconnection Technique” IBM Technical Disclosure Bulletin, IBM Corp. New York, US—vol. 32, no 3B, Aug. 1, 1989, pp. 294-299, XP000029849, ISSN: 0018-8689, figure 3.
Patent Abstract of Japan, JP 56 117495 A (Meisei Electric Co Ltd), Sep. 14, 1981 abstract; figures 1,3.
Patel Paresh
Teradyne, Inc.
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