Efficient switched capacitor integrator

Details Efficient switched capacitor integrator Efficient switched capacitor integrator

2000-03-17

2002-03-26

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C375S247000

Reexamination Certificate

active

06362761

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to interfaces, and, more particularly, to Digital/Analog (D/A) and Analog/Digital (A/D) conversions.
BACKGROUND OF THE INVENTION
D/A and A/D conversions are important interface processes that find applications in telecommunication, audio systems, instrumentation and the like. These processes continuously demand highly precise filters, such as the switched capacitor filters whose basic element is the integrator. Therefore, a particularly efficient integrator may be very useful for the above-cited applications.
By way of example, consider the application of a sigma-delta (&Sgr;&Dgr;)D/A converter for low-pass signals whose basic scheme is as shown in FIG.
1
. In these types of converters, the &Sgr;&Dgr; modulator converts an N bit digital signal into a 1-bit signal, shifting the quantization noise thus introduced outside the signal band. The low-pass analog filter would then eliminate this noise. The purpose of a 1-bit DAC is to form the interface between the digital world, represented by the bit-stream output delivered by the modulator, and the analog world, represented by the switched capacitor low-pass filter.
FIG. 2
shows the output of the 1-bit DAC in detail. Specifically,
FIG. 2
shows how the energy that corresponds to the logic level 1 is different from the one that corresponds to the level 0. The figure also shows how the energy of two consecutive
1
s is different from the energy that may be obtained by adding two nonconsecutive 1s. For these reasons, switched capacitor filters are preferred because what is considered important is the value assumed by the signal of
FIG. 2
at a specific instant.
FIG. 2
also shows the effect in time of unwanted noise, as generated by the voltage references V
h
V
l
, that becomes superimposed on the useful signal. In frequency, the high frequency noise contained in the input signal is eventually folded back in the band, thus determining a notable degradation of the total signal
oise ratio, as shown in FIG.
3
. The effect of folding back the noise inside the band is even more evident as the noise that superimposes the signal, delivered as output by the 1-bit DAC, depends on the bit-stream. Indeed, the expression for the filter's output voltage is given by:
V
OUT
=
V
ref
·
K
2
N
-
1
·
α
⁡
(
K
)
+
C
(
1
)
where:
K:input word to the DAC (O≦K≦2
N
−1);
N:number of bits of the converter;
C:constant that allow the curve to be translated;
&agr;(K):variable, K dependent, which expresses the perfect linearity of the converter;
V
ref
∝V
h
-V
l
: reference voltage.
Equation 1 demonstrates that the existence of a nonlinearity introduces a multiplying factor of V
ref
, thus causing a distortion effect.
In the case of a 1 bit converter (N=1) shown in
FIG. 1
, the system is always linear (&agr;(K)=1∀K) as long as V
ref
is perfectly stable and free of components whose frequency is different from 0. If this were not the case, such components would modulate the spectrum components of the input signal, thus determining a distortion effect.
Hence, there is a need for an efficient switched capacitor integrator structure, which permits the realization of the desired filters without introducing excessive and undesired noises on the reference voltages V
h
e V
l
.
The 1-bit DAC is often directly integrated inside the following switch capacitor filter, especially for those applications to be integrated on a single chip. Since the integrator is usually the basic element of a filter, there exist different structures that permit the 1-bit DAC to link to the integrator itself. Depicted in
FIG. 4
is a conventional structure of a switched capacitor integrator with a stray-insensitive connection of the input capacitance C
11
.
FIG. 5
shows a known evolution of the integrator of
FIG. 4
, which doubles the dynamic of the output signal by using a fully differential structure. The capacitances C
a
, C
b
, C
c
and C
d
represent the parasitic capacitances of the capacitors C
1
and C
11
, realized on the silicon. Typically, one of these two parasitic capacitances is much bigger than the other because the distance between one of the two plates and the substrate connected to ground is shorter.
By putting V
din
=2·(V
h
-V
l
), we have:
V
dout
⁡
(
n
)
=
V
dout
⁡
(
n
-
1
)
-
C
11
+
C
b
/
2
C
1
·
V
din
⁡
(
n
-
1
)
·
(
-
1
)
K
(
2
)
where K=1 with bs=1 and K=0 with bs=0 (bs is the bit-stream).
Equation 2 is obtained upon considering the components of the circuit of
FIG. 5
as ideal components, with the exception of the capacitors to which are associated parasitic capacitances. In addition, the operational amplifier should be able to maintain the mean value of the outputs to a constant value in time. Furthermore, by indicating the asymptotic voltage on the input nodes of the operational amplifier as V
x
(∞) we have:
V
x
⁡
(
∞
)
=
2
·
C
11
·
V
com
+
(
V
h
+
V
1
)
·
C
b
2
·
(
C
11
+
C
b
)
(
3
)
Equation 2 and Equation 3 emphasize the need to minimize the capacitance C
b
, while the other parasitic capacitances are not involved, with the exception of C
c
which contributes in determining the time required by the system to obtain V
x
=V
x
(∞).
The fundamental problem of these approaches is that the capacitive load on the reference voltages V
h
e V
l
depends on the bit-stream; a condition that may introduce undesired distortion effects.
The scheme of
FIG. 6
was developed to avert this problem. This approach permits a constant load on the voltages V
h
and V
l
, regardless of the bit-stream value. The functioning characteristics of this modified scheme are identical to the ones shown in the scheme of FIG.
5
.
SUMMARY OF THE INVENTION
A switched capacitance integrator has now been devised which is particularly more efficient and suitable to realize filters without introducing significant noises on the nodes of the reference potentials of the integrator.
As compared to an earlier approach, e.g. identifiable in a scheme as the one shown in
FIG. 6
, the fundamental aspect of the present invention includes halving the whole input capacitance to be charged during an operating phase, and in carrying out the transfer of electric charge between the input switched capacitor and the capacitor of integration of one and the other feedback branch of the operational amplifier in a direct manner, that is, not referred to a common fixed potential as it is the case of known circuits. This reduces the strain on the operational a amplifier because the current delivered through an output node in order to discharge a capacitor is identical to the current delivered through the other output node that charges the other capacitor. Hence, there exists a unique current path, thus averting the effects caused by eventual mismatches between capacitances, unlike what happen in the known circuits of
FIGS. 5 and 6
in which the current path involves all four capacitors, that is, the pair of input capacitors and the pair of capacitors of integration, thus increasing the problems generated by the capacitive mismatch.


REFERENCES:
patent: 4599573 (1986-07-01), Senderowicz
patent: 5727024 (1998-03-01), Hauptmann
patent: 6184811 (2001-02-01), Nagari et al.

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