Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1997-03-10
1999-07-13
Monin, Jr., Donald L.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257207, 257664, 257691, 257923, H01L 2348
Patent
active
059230894
ABSTRACT:
A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.
REFERENCES:
patent: 4499484 (1985-02-01), Tanizawa et al.
patent: 4928164 (1990-05-01), Tanizawa
Shiffer et al., "A 473K Gate 0.7.mu. CMOS Gate Array," Proceedings of Fifth Annual IEEE International ASIC Conference, Sep. 21-25, 1992/Rochester, New York, pp. 443-446.
Nomura Shuji
Yamamoto Ichiro
Yao Chingchi
Kelley Nathan K.
Monin, Jr. Donald L.
Oki America Inc.
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