Efficient process tool utilization in semiconductor...

Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing

Reexamination Certificate

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C700S108000, C700S111000, C700S178000, C700S175000, C700S179000, C700S177000, C438S005000, C438S014000, C702S182000, C702S186000

Reexamination Certificate

active

06430456

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to manufacturing methods and, more particularly, to a method, system, and storage medium for increasing the efficiency of integrated circuit manufacturing by improving manufacturing equipment utilization.
2. Description of the Relevant Art
Manufacture of integrated circuits (ICs) upon semiconductor substrates (“wafers”) involves numerous pieces of equipment (“process tools”) and manufacturing steps. Evaluation of the quality of the ICs during manufacture is important to assure that the completed ICs will be functional. After each processing step, the quality of the ICs being manufactured could be evaluated; however, the number of steps is so large that it is not practical to evaluate after every step. Instead, evaluation occurs only after certain processing steps during manufacturing. Typically, not every wafer is evaluated but representative wafers are evaluated after a set number of wafers have been processed.
The evaluation of wafers typically includes making some type of measurement and then comparing the measurement result to an established acceptable range. The measurement can take many forms including inspection for quantity and type of defects on the surface of the wafer, measuring the response to electrical stimuli of various regions of the wafer, or determining the thickness and uniformity of a coating that has been deposited on the surface of the wafer. If the measurement result is found to be outside of the established acceptable range, one or more process tools are removed from use for manufacturing and these tools are referred to as being in the “down” state. Conversely, any process tool that is available for use is referred to as being in the “up” state.
In general, the processing flow of wafers is controlled by an automated factory system. This system is connected to the computers controlling the individual processing tools used in the IC manufacturing and the system also maintains a database of the current operating state of each tool. The system can accept a measurement result and can compare the result to a predetermined acceptable range and automatically place a process tool in the down state if the result is outside of the acceptable range. An example of an automated factory system is WorkStream™ sold by Consilium, Inc. of Mountain View, Calif.
Prior to a given measurement result being outside the acceptable range, many process tools may have been involved in the processing of the wafer. Multiple process tools therefore may have contributed to the result being outside the acceptable range. Some decision must be made as to which process tools to place in the down state. Generally, this decision is performed automatically by an automated factory system. The factory system is typically programmed to place the process tool most likely to have caused the result outside of the acceptable range in the down state. For example, certain types of defects on the wafer surface are often associated with a specific process tool. A potential difficulty occurs, however, if an incorrect process tool is placed in the down state. In such a case, the process tool in the down state, which is actually performing adequately, is not available for use while the process tool with an actual problem continues to produce defective ICs, thereby continuing to reduce efficiency and increase the cost of manufacturing.
During the time that a process tool is in the down state, personnel associated with the tool typically attempt to identify the problem and take corrective action. Once the problem is believed solved, the process tool may then be evaluated using test procedures, which may include usage of test wafers, to assure correct functioning before being placed back in the up state. A test wafer does not have functional ICs being manufactured upon it and, typically, is processed by only a single process tool and then evaluated to determine the functioning of that process tool.
The process tool, however, may not process test wafers in the exact same manner as product wafers, which are wafers upon which functional (sellable) ICs are being manufactured. The test wafers therefore may not be sensitive to a problem that could cause defective ICs to be manufactured. Although the test wafer may be found to be acceptable and the process tool placed in the up state, subsequent product wafers processed by the process tool may not be acceptable. It could be that the original problem, to which the test wafer is not sensitive, has not been corrected or that the original problem has been corrected but a new problem, to which the test wafer is not sensitive, has been created accidentally. For either case, defective ICs are produced resulting in reduced efficiency and increased cost of manufacturing.
Measurement results being outside the acceptable range can also be due to the integration or combination of manufacturing steps between process tools (often referred to as an “integration issue”) instead of being due to a single tool. The state in which a process tool leaves a wafer can affect subsequent processing steps by other process tools. Any evaluation of a given process tool using a test wafer will not detect such a problem since the test wafer is processed by only the single tool. That process tool will then be placed back in the up state, but the original problem still may not have been addressed.
Measurement results being outside the acceptable range can sometimes cause process tools to be placed in the down state for problems that ultimately do not affect the functioning of the ICs. For example, certain process tools can induce defects on wafer surfaces in areas of the wafer that will not affect the performance of the completed ICs. These nuisance defects, however, will cause the process tool to be placed in the down state, necessitating personnel associated with the tool investigating for problems and then running test wafers before placing the process tool back in the up state. This results in a process tool that was performing adequately unnecessarily being removed from manufacturing for a period of time.
Individual process tools are also subject to routinely scheduled tests as an additional check on the tool's performance. Such tests are typically performed using test wafers so that the performance of the individual tool may be isolated. If the process tool fails the test, it is immediately placed in the down state. During the time that the process tool is down, personnel associated with the tool attempt to determine the problem and take corrective action. Once the process tool passes the test it previously failed, the process tool is often placed in the up state. No evaluation is necessarily made at this time, however, to ensure that product wafers are being processed correctly. Although the original problem was corrected, a new problem or integration issue, to which the test wafer is not sensitive, could have been created accidentally.
If a process tool is repeatedly placed in the down state unnecessarily, there may be a reduction in the responsiveness and efficiency of the personnel associated with that tool. After a process tool is continually placed in the down state unnecessarily, for example, it may become routine for personnel to run a test wafer and place the tool back in the up state without even examining the tool. When an actual problem with the process tool occurs, the tool may be placed back into the up state if the test wafer is not sensitive to the problem. In this case, defective ICs will continue to be produced by the process tool.
Anytime a process tool is placed in the down state and thereby removed from production there is a decrease in efficiency and increase in cost of manufacturing ICs; however, a process tool producing defective ICs while remaining in the up state also causes a decrease in efficiency and increase in cost. It is also important to ensure that any process tool returned to the up state is not producing defective ICs. It is therefore desirable to develop an improved method o

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