Efficient polling technique using cache coherent protocol

Details Efficient polling technique using cache coherent protocol Efficient polling technique using cache coherent protocol

1994-12-14

1997-03-11

Chan, Eddie P.

395866, 395727, 395483, G06F 1316

Patent

active

056110740

ABSTRACT:
An efficient polling technique to attain improved system performance preserves the concept of polling, but instead of polling across system buses to the device, a poll is made within the processor's cache structure, which is typically internal to the processor complex or attached on a local isolated bus. The polling status location is mapped in the cachable address space of the processor. Hence, the polling occurs to a normal cachable location. When the device completes its task, it signals to the polling loop by invalidating the cache line corresponding to the poll location. The next time software tries to read the status value, the processor misses in its cache and automatically reloads the updated status value from the device. This causes the polling loop to exit and normal processing continues. The only bus traffic that results is that which is issued by the device to signal cache line invalidation and a subsequent processor initiated cache line reload. Hence, the bus is totally available for all agents while the processor is within the polling loop.

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