Efficient parallel testing of integrated circuit devices...

Details Efficient parallel testing of integrated circuit devices... Efficient parallel testing of integrated circuit devices...

1999-03-01

2002-09-17

Sherry, Michael (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C714S736000

Reexamination Certificate

active

06452411

ABSTRACT:

BACKGROUND INFORMATION
This invention is related to the testing of integrated circuit devices using a semiconductor tester, and more particularly to testing a number of devices in parallel.
Integrated circuit (IC) devices are an important part of almost every modern electronic or computer system. To reduce the manufacturing cost of such systems, the manufacturer expects each constituent IC device to be virtually free of defects and to perform according to its specifications. Thus, it is not unusual to expect that every IC device is subjected to rigorous testing prior to being shipped to the system manufacturer.
It has been determined, however, that a significant portion of the total cost of producing an IC device can be attributed to its testing. That is because many modern IC devices perform complex functions, have a large number of inputs and outputs, and operate at high speeds. For instance, a 256 Mb memory device may have 16 data lines and 22 address lines. A simplistic approach to test such a device would be to write a known data value to each memory location, read from the location, and then compare the value read to the written value (expected value) to determine any negative results (errors). However, because of the large number of locations, each containing several bits, such a technique of testing each bit and combination of bits at each location is expensive and time consuming. The field of test engineering has developed to create efficient techniques for detecting as many errors as possible while using the least number of test sequences.
A memory device may be tested using an automated semiconductor tester.
FIG. 5
shows such a tester
502
having a number (N) of channels for parallel testing of a number of devices under test
518
(DUTs.) The DUT
518
may have a memory cell array and built-in self test (BIST) circuitry. The tester
502
normally executes a test program and in response generates data and addresses which define a test sequence
506
engineered for testing the particular DUTs. The data and addresses on each channel of the tester are fed to a respective DUT, so that a number of DUTs, corresponding to the number of channels, may be tested simultaneously. A probe card (not shown) receiving all N channels delivers address and write data of the test sequence to locations in the N different DUTs simultaneously. The tester
502
can read the data from the locations in the DUTs for comparison with expected data. This may occur while the DUTs are still part of the semiconductor wafer
516
as shown. The results of the comparison help determine whether some portion of the device is functioning improperly, for example whether a particular bit read from a location in the memory device is in error. The tester performs the above read and write cycles many times with the same or different data patterns to verify as many locations of the DUTs as possible given time and budget constraints.
To increase the throughput of the test system in terms of the number of DUTs tested per unit time, a larger tester may be built with more channels. Such a solution, however, could be prohibitively expensive. The tester
502
is a complex and high speed machine, requiring much time and expense to modify or improve. Moreover, a single channel of a modern tester may comprise between 50 to 100 signal wires, such that increasing the number of channels between the tester and the probe card will make it physically impractical to connect all of the signal wires to the probe card. Therefore, a more efficient solution for increasing the throughput of an IC test system is needed.
SUMMARY
According to an embodiment of the invention, a test apparatus is disclosed that contains a trusted location that holds a reference copy of test information, and a test circuit that has an interface to the trusted location. In combination with the test apparatus, a connection may be provided for the test circuit to access a number of DUTs, and to test each DUT based on the reference, copy obtained form the trusted location. The test circuit may snoop a connection between a test host and the trusted location, and can identify commands on the connection and interpret them for local action. For instance, the test apparatus may include intermediate test circuitry positioned between a semiconductor tester and the DUTs. The intermediate circuitry obtains valid data from the trusted location, e.g., in a known good device, and compares the valid data with data read from the DUTs to determine the error status of the DUTs. The results of the test may then be communicated to the test host.
The test host may itself issue commands to the test circuit to configure the local action. The test circuit includes logic means for detecting these commands, and for managing local test functions. The latter may include propagating writes to one or more connected DUTs in parallel, in response to having snooped writes to the trusted location. When the DUTs have memory circuitry to be tested, the test circuit may also manage the memory circuitry as needed by, for instance, applying refresh cycles.
A particular embodiment is a system having a tester, a known good device, a channel coupled between the tester and the known good device for data communication between the known good device and the tester, and interface circuitry for monitoring the channel. The tester writes data as part of a test sequence to locations in the known good device and subsequently reads data from corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is writing and reading to and from the locations in the known good device and in response performs a write or read from corresponding locations in the DUTs. The interface circuitry may also make comparisons between data from the known good device and data from the DUTs.


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