Efficient muxing scheme to allow for bypass and array access

Details Efficient muxing scheme to allow for bypass and array access Efficient muxing scheme to allow for bypass and array access

2005-02-09

2008-12-16

Nguyen, Steven H. D (Department: 2619)

Multiplex communications

Fault recovery

Bypass an inoperative station

C370S535000, C710S023000, C711S138000, C711S207000

Reexamination Certificate

active

07466647

ABSTRACT:
A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.

REFERENCES:
patent: 5421000 (1995-05-01), Fortino et al.
patent: 5572535 (1996-11-01), Pixley et al.
patent: 5828475 (1998-10-01), Bennett et al.
patent: 6233652 (2001-05-01), Mathews et al.
patent: 6549997 (2003-04-01), Kalyanasundharam
patent: 6594728 (2003-07-01), Yeager
patent: 2004/0162961 (2004-08-01), Lyon

Affiliated with

Also associated with

Rating

Efficient muxing scheme to allow for bypass and array access does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Efficient muxing scheme to allow for bypass and array access, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient muxing scheme to allow for bypass and array access will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4038186