Efficient multiplexer structure for use in FPGA logic blocks

Details Efficient multiplexer structure for use in FPGA logic blocks Efficient multiplexer structure for use in FPGA logic blocks

1998-06-22

2000-02-01

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

327565, 326 41, H03K 17693

Patent

active

060207760

ABSTRACT:
The invention provides a multiplexer structure having an efficient quadrilateral layout. The multiplexer structure includes a first multiplexer and a second multiplexer, both being coupled to receive a plurality of common input signals. Each multiplexer has a first stage and a second stage. The first stages of the first and second multiplexers are fabricated in a plurality of adjacent multiplexer stripes. Each multiplexer stripe includes a plurality of interleaved pass transistors. The multiplexer stripes are fabricated in parallel with each other along a first axis. Gate electrodes of the pass transistors extend in parallel with each other along a second axis that is perpendicular to the first axis. One or more rows of memory cells extend along the second axis, adjacent to the multiplexer stripes. These memory cells control the pass transistors in the multiplexer stripes. The second stages of the first and second multiplexers are fabricated in a multiplexer row, which extends along the second axis and includes a plurality of interleaved pass transistors. One or more additional rows of memory cells extend along the second axis, adjacent to the multiplexer row. These memory cells control the pass transistors in the multiplexer row. The multiplexer stripes, memory cell rows, and multiplexer row all have quadrilateral layouts. In addition, the entire multiplexer structure has a quadrilateral layout.

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