Efficient multi-threaded multi-processor scheduling...

Details Efficient multi-threaded multi-processor scheduling... Efficient multi-threaded multi-processor scheduling...

2007-07-24

2007-07-24

Ho, Duc (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S413000, C711S100000

Reexamination Certificate

active

10170409

ABSTRACT:
A system and method of scheduling packets in a multi-threaded, multiprocessor network architecture provides enhanced speed and performance. The architecture involves a scheduler thread that transitions between queues in response to a depletion of queues by a weighted amount, a plurality of transmit threads that deplete the queues by the size of packets transmitted and a plurality of receive threads that initialize the weights for idle queues.

REFERENCES:
patent: 6978460 (2005-12-01), Arakawa
patent: 2002/0021707 (2002-02-01), Sampath et al.
patent: 2003/0018691 (2003-01-01), Bono
patent: 2003/0133406 (2003-07-01), Fawaz et al.

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