Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2000-09-25
2004-04-20
Rao, Andy (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C375S240210
Reexamination Certificate
active
06724822
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is applicable to the implementation of a digital video format down-conversion for use in digital video decoder. Typical applications of this invention include HDTV decoding, video conferencing and picture-in-picture systems.
2. Description of the Prior Art
Low-resolution digital video decoders have received considerably attention lately in academia and industry. In a digital video decoding system, the format down-conversion can be achieved by decimating the decoded full-resolution video sequences. Reconstructed video with good quality can be obtained by using this method. However, the decimation of decoded video sequences adds complexity to the full-resolution video decoding. In order to reduce the amount of computation, the memory size and other constrains such as memory bandwidth and clock rates incurred by this approach, image decimation has to be realized in the earlier stage of the decoder, for example, inside the decoding loop.
An effective method for the digital video format down-conversion has been invented and filed in Japan on Jun. 8, 1999, entitled “A generalized orthogonal transform method for low-resolution video decoding”, with application No. H11-160876, and assigned to Matsushita Electric Industrial Co. Ltd., which is herein enclosed by reference.
FIG. 1
shows a block diagram of this video format down-conversion method. The details of the system operation and the orthogonal kernels were discussed in the above-mentioned application. In this architecture, the low-resolution pixels stored in the frame buffer are interpolated and decimated using orthogonal transform basis functions before and after the full-resolution motion compensation. The interpolation and decimation filters play a very important role in controlling the error propagation introduced by picture decimation of the format down-conversion system of digital video. In the format down-conversion system of digital video shown in
FIG. 1
, these filters are realized using a number of orthogonal transform kernels. One example for the orthogonal transform kernels used for video down-conversion with the decimation ratio of 8:3 are illustrated in FIG.
2
. The direct computation architecture of the interpolation and decimation filtering operations based on these kernels are shown in FIG.
3
. Since the coefficients of the kernels are simple, the implementation of the system is relatively easy compared to the conventional digital video format down-conversion methods. Simulation results show that this method is also very effective in error propagation control.
SUMMARY OF THE INVENTION
The digital video format down-conversion method using orthogonal transform described in the prior art generates high quality down-converted video. Although the transform kernels consists of simple coefficients, more efficient implementation method for efficient computation of the orthogonal transforms is still needed in order for the system to handle high bit rate video decoding, such as HDTV decoding. The problem to be solved by the current invention is to establish efficient computation architecture for the interpolation and decimation filtering processes to achieve effective motion compensation for the digital video format down-conversion system mentioned in the prior art.
In order to solve the above-described problem, efficient computation architecture for implementing interpolation and decimation filters used by the digital video format down-conversion system is invented. The computation architecture comprises a frequency component computing section, a coefficient weighting section and a pixel reconstruction section. Less computational operations are required compared to the direct implementation of the orthogonal transform kernels described in the prior art.
The frequency component computing section is used to transform the input into frequency domain to generate the transform coefficients. The coefficient weighting section is used for receiving transform coefficients and generating weighted transform coefficients. The weighted transform coefficients are finally transformed into spatial domain to generate the filtered pixels having different resolution from the original pixels.
The operation of the computation architecture for the interpolation and decimation filtering processes is now explained. The original pixels are transformed into frequency domain by the frequency component computing section to generate the transform coefficients. The transform coefficients are multiplied by a set of pre-determined constants by the coefficient weighting section to generate the weighted transform coefficients. The weighted transform coefficients are transformed from frequency domain into spatial domain by the pixel reconstruction section to provide filtered pixels which have different resolution from the original pixels.
The operations of the frequency component computing section are now explained. A reversed sequence of a block of the original pixels is generated in upper or lower address reversed order. A pair of selected pixel sequences is selected from the pixel sequence, the reversed sequence, the transform coefficients and the bit-shifted coefficient sequence by a pixel selecting section. An operation indication sequence is generated by the pixel selecting section to indicate the adding or subtracting operation. The sum or difference of the pair of selected pixel sequences is computed based on the operation indication sequence to generate the transform coefficients. Each transform coefficient is shifted by one or more bits to generate the bit-shifted coefficient sequence.
The frequency component computing section can also be operated using another method described here. The data address reversing section provides a reversed data set of a block of the original pixels in upper or lower address reversed order. A data selecting section receives the original pixels and the reversed data set to provide an operation indication set and two selected data sets. The calculator computes sum or difference of each pair of the selected data to generate processed data. One or more cascaded arithmetic units receives the processed data, manipulates them algebraically to provide the transform coefficients.
The operations of the coefficient weighting section are now explained. Each transform coefficient is multiplied by one of the pre-determined constant values stored in the coefficient memory. The output of the multiplying section or the transform coefficients are switched based on a coefficient bypass control signal to provide the weighted transform coefficients. The coefficient bypass control signal is determined based on the transform kernels used for the format down-conversion system of digital video.
The operations of the pixel reconstruction section are now explained. The weighted transform coefficients are shifted by one or more bits to generate the bit-shifted vector. A pair of selected coefficient vectors is selected from the coefficient vector, the bit-shifted vector, filtered pixels and reversed pixel vector by a coefficient selecting section. An operation indication vector is generated by the coefficient selecting section to indicate the adding or subtracting operation. The sum or difference of the pair of coefficient samples is computed based on the operation indication vector to generate the filtered pixels. The reversed pixel vector of a block of filtered coefficients is generated by an address reversing section in upper or lower address reversed order.
The pixel reconstruction section can also be realized using one or more cascaded arithmetic units. The operations of the arithmetic units used for the frequency component computation section and pixel reconstruction section are now explained. The shifter shifts the input data by one or more bits to generate bit-shifted data set. The data selector receives the input data and the bit-shifted data set to provide an operation indication set and two selected data sets. A calculator adds or subtracts two selected data set
Bi Mi Michael
Kiew Peter Kwong Ming
Matsushita Electric - Industrial Co., Ltd.
Rao Andy
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