Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2003-03-13
2004-10-19
Pascal, Robert (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C375S297000
Reexamination Certificate
active
06806780
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to phase locked loops, and more particularly to a system and method of efficient modulation compensation of a &Sgr;&Dgr; fractional phase locked loop.
2. Description of the Prior Art
A &Sgr;&Dgr; fractional phase locked loop (PLL) has to filter its associated quantization noise. This filtering creates a limited system bandwidth that undesirably filters the modulated data, degrading the Bit Error Rate (BER). A predistortion filter is generally employed to compensate for the limited system bandwidth and to provide a global flat transfer function (TF). Because integrated circuit (IC) process variations as well as other parameters (e.g. supply, temperature, transmit target frequency and the like) modify the PLL TF, the TF needs to be measured prior to any transmission in order to compute the requisite predistortion filter.
The TFs associated with known PLLs have many variable parameters. Further, the perturbation that is sent to estimate the associated TF must cover all frequency ranges of interest, and is usually a pulse (time Dirac=uniform power spectrum density). This technique has numerous shortcomings related to time and computation limiting constraints. Some of these shortcomings include 1) the impulse phase response of the PLL can be long; 2) the impulse phase response is not synchronous with the reference clock; 3) the impulse phase response is difficult to measure with on-chip circuitry; and 4) the Inverse Laplace Transform (ILT) of the response has a heavy computational burden, often requiring DSP interruptions.
In view of the foregoing, it is highly desirable and advantageous to have a fast, simple, accurate, on-chip tuning scheme to achieve modulation compensation of a &Sgr;&Dgr; fractional PLL that eliminates the foregoing shortcomings associated with known PLLs.
SUMMARY OF THE INVENTION
The present invention is directed to a technique for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, K
pll
, of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF. This technique is advantageous over the prior art since it 1) provides a very short perturbation response from the system to measure its associated TF, reducing the lock time of the transmit PLL;, which is a critical parameter according to any wireless standard; and 2) enables a simple on-chip measurement of the perturbation response, as well as a straightforward design of the compensation filter.
The foregoing technique therefore provides a fast, simple, accurate, on-chip tuning scheme for modulation compensation of a &Sgr;&Dgr; fractional PLL in which 1) the required response time is the tone period (in fact half the period); 2) the tone period can be coherent with a reference clock (synchronous); 3) the impulse phase response is easier to measure at one low frequency; and 4) no computationally intense ILT must be computed.
According to one embodiment, a method for characterizing a phase locked loop (PLL) transfer function comprises the steps of specifying a PLL having a transfer function defined in terms of a PLL gain and a plurality of time constants associated with the loop filter, setting the PLL transfer function poles and zeros to fixed values, independent of process and temperature variations such that unknown PLL parameters are reduced to solely the PLL gain; measuring a low frequency modulated single frequency modulated tone signal via the PLL, and generating a perturbation response thereto; estimating an attenuation factor based on the perturbation response; and characterizing the PLL transfer function associated with the attenuation factor, wherein the attenuation factor determines the PLL gain.
According to another embodiment, a method for characterizing a phase locked loop (PLL) transfer function that is dependent solely on the PLL gain K, comprises the steps of measuring a low frequency modulated single frequency modulated tone signal via the PLL, and generating a perturbation response thereto; estimating an attenuation factor based on the perturbation response; and characterizing the PLL transfer function associated with the attenuation factor, wherein the attenuation factor determines the PLL gain K.
According to yet another embodiment of the present invention, a phase locked loop (PLL) predistortion filter comprises an uncompensated filter; and a weighted predistortion filter, wherein the PLL predistortion filter comprises the sum of the uncompensated filter and the weighted predistortion filter, and further wherein the predistortion filter has only fixed coefficients that do not require computation in association with a tuning block.
According to still another embodiment of the present invention, a predistortion filter comprising an uncompensated PLL filter summed with a weighted predistortion filter, wherein the predistortion filter comprises fixed coefficients that are substantially independent of process, voltage and temperature variations, and further comprises no more than one variable element.
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Daniel R. McMahill and Charles G. Sodini, A 2. 5-Mb / s GFSK 5. 0 -Mb / s 4 -FSK Automically Calibrated —Frequency Synthesizer IEEE Journal of Solid State Circuits, vol. 37, No. 1, pp. 18-26, Jan. 2002.
Bakkaloglu Bertan
Bellaouar Abdellatif
Fontaine Paul H.
Brady III Wade James
Chang Joseph
Neerings Ronald O.
Pascal Robert
Telecky , Jr. Frederick J.
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