Efficient method of PMOS stacked-gate memory cell...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180

Reexamination Certificate

active

06903979

ABSTRACT:
A method of programming a PMOS stacked gate memory cell is provided that utilizes the correlation between injection current and substrate current during the programming cycle to provide a feedback correction to the control gate of the memory cell to compensate for the negative potential shift on the floating gate as a result of its charging time.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 5487033 (1996-01-01), Keeney et al.
patent: 5566111 (1996-10-01), Choi

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