Efficient method for fabricating optimal BiCMOS N-wells for bipo

Details Efficient method for fabricating optimal BiCMOS N-wells for bipo Efficient method for fabricating optimal BiCMOS N-wells for bipo

1994-06-06

1995-11-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 57, 437 59, 437 74, H01L 21265, H01L 2170, H01L 2700, H01L 21302

Patent

active

054707668

ABSTRACT:
A BiCMOS process is provided for fabricating on the same semiconductor substrate three types of N-wells optimized respectively for (i) PMOS FETs requiring low P+/N-well capacitance; (ii) NPN bipolar transistors which do not require low collector-to-substrate capacitance and PMOS FETs which require latch-up immunity; and (iii) NPN bipolar transistors which require low collector-to-substrate capacitance.

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