Efficient management method of memory cell array

Details Efficient management method of memory cell array Efficient management method of memory cell array

2001-01-22

2003-08-19

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S049130, C711S003000, C711S104000, C711S128000

Reexamination Certificate

active

06608793

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of efficiently managing a memory cell array, and more particularly, a memory cell array management method for efficiently accessing a memory.
2. Description of the Related Art
Conventionally, in a DRAM memory operation, a memory row cycle operation during which the longest running time is spent is responsible for restraints of performance of the DRAM memory, and execution of a random row cycle causes deterioration in performance of the memory. For this reason, as a solution for minimizing a running time required for processing the random row cycle, an attempt to reduce the running time itself of the random row cycle and an attempt to substitute an operation on which a short running time is spent relatively for the memory row cycle operation on which the longest running time is spent have been made. A typical example of the former includes a sub-word line method in which in order to reduce a time needed for activating a word line occupying the most part among the running time of the random row cycle, a long word line is divided into various sub-word lines and an RC time constant is minimized to shorten a driving time (T. Sugibayashi, et al., “A 30 ns 256-Mb DRAM with a Multi divided Array Structure” IEEE Journal of Solid State Circuit, pp1092-1098. November, 1993 and T. Murotani, et al., “Hierarchical Word Line Architecture for Large Capacity DRAM” IEICE Trans. Electron., pp550-556, April, 1997).
In the meantime, examples of the latter includes a multi bank method in which a memory have a plurality of memory banks each being accessed and execution of each alternating with each other, an EDRAM (Enhanced DRAM) method in which an SRAM having a storage capacity of one page is disposed around a memory sense amplifier, and if there occurs a cache hit, a row cycle is removed to accomplish improvement in performance of a memory, a CDRAM (Cache DRAM) method in which an SRAM for performing a high speed operation is integrated with a DRAM, and if there occurs a cache hit, the row cycle is removed.
However, in the above mentioned methods, for a DRAM, as its storage capacity is increased, a capacity of a cell included in the identical memory bank is increased, particularly, an increase in capacity of a memory cell activated by one word line leads to a unnecessary increase of an activated page, which is a main fact of power consumption.
Such problems can be found from Table 1.
Operating
*8, 4 Bank
Row Add
Bank Add
Col Add
Current*
 64 Mb
RA0- RA11
BA0, BA1
CA0-CA8
 95 mA-115 mA
128 Mb
RA0- RA11
BA0, BA1
CA0-CA9
115 mA-150 mA
256 Mb
RA0- RA12
BA0, BA1
CA0-CA9
115 mA-140 mA
As shown in Table 1, it can be more apparently seen that a current consumption according to an increase of a column address is greater than that according to an increase of a row address.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a method of efficiently managing a memory cell array in which deterioration in performance of a memory is prevented in the process of executing a random row cycle.
Another object of the present invention is to provide a method of efficiently managing a memory cell array in which performance of a memory system is improved by reducing the frequency itself of generation of a random row cycle requiring a long running time.
Another object of the present invention is to provide a method of efficiently managing a memory cell array in which a unnecessary activation of a sense amplifier is prevented to reduce a power consumption of a memory system, thereby improving efficiency in operation and performance of the memory system.
In order to achieve the above objects, the present invention is characterized in that four memory cell array management method, i.e., a partial segment activation method, an adaptive window control method, an associative mapping method, and an enhanced bank interleaving method are used respectively, or a combination of them is used, thereby reducing a power consumption and improving performance of a memory system. That is, in management of the memory cell array, an upper level operation type using a segment as a unit is employed.
In a method of efficiently managing a memory cell array according to the present invention, only some sub-word lines after activation of a main word line are activated, and then a window including a memory cell array connected with the activated sub-word lines is activated and managed. Then, a memory address region included in the window is mapped.


REFERENCES:
patent: 5657469 (1997-08-01), Shimizu
patent: 5774409 (1998-06-01), Yamazaki et al.

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