Efficient local-bus ROM memory for microprocessor systems

Static information storage and retrieval – Addressing – Using selective matrix

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365103, 36523003, G11C 802

Patent

active

054775035

ABSTRACT:
An efficient technique for providing ROM memory on a microprocessor local bus is described whereby a ROM and all necessary address decoding and control circuitry is incorporated in a single integrated circuit. By doing this, only one chip is required to add ROM to a microprocessor local bus, saving considerable space and power over discrete implementations. The ROM is implemented in a wide memory format, matching the bus width of the microprocessor to which it is connected. This permits full-speed access to the local bus ROM, and eliminates any need for such techniques as ROM "shadowing".

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