Efficient interface for the main store of a data processing syst

Details Efficient interface for the main store of a data processing syst Efficient interface for the main store of a data processing syst

1988-12-16

1991-08-27

Olms, Douglas W.

Boots, shoes, and leggings

364200, G06F 100

Patent

active

050439375

ABSTRACT:
A memory interface mechanism is driven from the memory controller side which comprises lines which are shared by the memory user devices and lines which are specific to the memory user devices. The shared lines are the address and data bus lines the byte select lines, the data and address clock lines and the last operation line. The specific lines are the request lines, the address user indicator lines and data user indicator lines. A user initiates a memory operation by activating its request line and then waits for the activation by the memory interface control circuit for the activation of the address and data user indicator lines. The user controls the address and data transfer count and ends the transfer by activating the last operation line. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven which allows full advantage to be taken of a page mode facility of the memory. The memory operations may be pipelined since servicing a request from a user may be started before servicing the request from the previous selected user is ended.

REFERENCES:
patent: 3925766 (1975-12-01), Bardotti et al.
patent: 4028663 (1977-06-01), Royer et al.
patent: 4080652 (1978-03-01), Cronshaw et al.
patent: 4330844 (1982-05-01), Dubuc
patent: 4453214 (1984-06-01), Adcock
patent: 4607348 (1986-08-01), Sheth

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