Efficient instruction prefetch mechanism employing selective...

Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching

Reexamination Certificate

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C712S241000

Reexamination Certificate

active

07085916

ABSTRACT:
For use in a processor having an external memory interface, an instruction prefetch mechanism, a method of prefetching instructions and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a branch predictor that predicts whether a branch is to be taken, (2) prefetch circuitry, coupled to the branch predictor, that prefetches instructions associated with the branch via the external memory interface if the branch is taken and prefetches sequential instructions via the external memory interface if the branch is not taken and (3) a loop recognizer, coupled to the prefetch circuitry, that determines whether a loop is present in fetched instructions and reinstates a validity of instructions in the loop and prevents the prefetch circuitry from prefetching instructions outside of the loop until the loop completes execution.

REFERENCES:
patent: 4910664 (1990-03-01), Arizono
patent: 4965722 (1990-10-01), Tokuume
patent: 5784603 (1998-07-01), Leung et al.
patent: 5835435 (1998-11-01), Bogin et al.
patent: 6243807 (2001-06-01), Chi

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