Data processing: database and file management or data structures – Database design – Data structure types
Reexamination Certificate
1999-03-31
2002-12-24
Jung, David (Department: 2175)
Data processing: database and file management or data structures
Database design
Data structure types
C714S047300, C709S249000
Reexamination Certificate
active
06499028
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of computer systems and more particularly to the monitoring of memory performance in a non-uniform memory architecture system.
2. History of Related Art
The use of multiple processors to improve the performance of a computer system is well known. In a typical arrangement, a plurality of processors are coupled to a system memory via a common bus referred to herein as the system or local bus. The use of a single bus ultimately limits the ability to improve performance by adding additional processors because, after a certain point, the limiting factor in the performance of a multiprocessor system is the bandwidth of the system bus. Generally speaking, the system bus bandwidth is typically saturated after a relatively small number of processors have been attached to the bus. Incorporating additional processors beyond this number generally results in little if any performance improvement.
Distributed memory systems have been proposed and implemented to combat the bandwidth limitations of single bus systems. In a distributed memory system, two or more single bus systems referred to as nodes are connected to form a larger system. Each node typically includes its own local memory. One example of a distributed memory system is referred to as a non-uniform memory architecture (NUMA) system. A NUMA system is comprised of multiple nodes, each of which may include its own processors, local memory, and corresponding system bus. The memory of each node is accessible to each other node via a high speed interconnect network that links the various nodes. The use of multiple system busses (one for each node) enables NUMA systems to employ additional processors without incurring the system bus bandwidth limitation experienced by single bus systems. Thus, NUMA systems are more suitably adapted for scaling than conventional systems.
In a NUMA system, the time required to access system memory is a function of the memory address because accessing memory local to a node is faster than accessing memory residing on a remote node. In contrast, access time is essentially independent of the memory address in conventional SMP designs. Software optimized for use on conventional machines may perform inefficiently on a NUMA system if the software generates a large percentage of remote memory accesses when executed on the NUMA system. The potential for performance improvement offered by scaleable NUMA systems may be partially offset or entirely negated if, for example, the paging scheme employed by the NUMA system allocates a code segment of the software to the physical memory of one node and a data segment that is frequently accessed by the processors of another node. Due to variations in memory architecture implementation, paging mechanisms, caching policies, program behavior, etc., tuning or optimizing of any given NUMA system is most efficiently achieved with empirically gathered memory transaction data. Accordingly, mechanisms designed to monitor memory transactions in NUMA systems are of considerable interest to the designers and manufacturers of such systems.
SUMMARY OF THE INVENTION
Accordingly, it is an objective of the present invention to provide a performance monitor configured to count and categorize memory transactions in a computer system. In one embodiment, the monitor is connected directly to the computer system's interconnect network. In an alternative embodiment, the monitor may be connected to the system bus of a node on the computer system. The monitor may be suitably implemented with commercially available programmable gate arrays and packaged as a circuit board that includes connector sockets suitable for permitting the monitor to tap into the interconnect network. In an embodiment in which the monitor is coupled to the interconnect network, the monitor may include a I/O interface for communicating with the computer system via a standard I/O bus such as a PCI bus. In an embodiment in which the monitor resides on a system bus, direct communication with the computer may be achieved via the system bus thereby eliminating the need for an I/O bus interface.
Broadly speaking, a first application of the invention emphasizing the ability to separately monitor concurrently executing programs contemplates a computer system comprised of a local node including at least one processor coupled to its local memory via a local bus of the local node. A remote node of the system includes at least one processor coupled to a memory local to the remote node via a local bus of the remote node. An interconnect network couples the remote node to the local node such that the processor of the local node can access memory local to the remote node and the processor of the remote node can access memory local to the local node. The system further includes a performance monitor including an interface coupled to the interconnect network and configured to extract, at a minimum, physical address information from a transaction traversing the interconnect network, a filter module adapted for associating the physical address with one of multiple memory blocks, and an address mapping module configured to associate the appropriate memory block with one or more access counters. The performance monitor is preferably configured such that each access counter is associated with a memory region owned by a program thereby providing means for counting memory transactions associated with the program.
The first application of the invention further contemplates a performance monitor that includes an interface, a filter module, and an address mapping module. The interface is suitable for coupling to an interconnect network of a computer system or to a system bus of a node within the computer system depending upon the location of the monitor. The interconnect network links a local node of the system with at least one remote node. The interface is configured to extract, at a minimum, physical address information from a transaction traversing the network or bus to which the monitor is coupled. In addition to physical address information, other pertinent information such as transaction type information and node identification information may be contained in and extracted from the transaction. The filter module associates the physical address with one of several memory blocks, where each memory block corresponds to a contiguous portion of the system's physical address space. The address mapping module associates the identified memory block with one or more access counters and increments each of the associated access counters where each access counter corresponds to one of multiple concurrently executing programs. The association between the selected memory block and the access counters is facilitated by a pointer field corresponding to each memory block.
In one embodiment of the performance monitor, the interface unit may be configured, such as by the appropriate setting of a direction selection bit in a performance monitor status register, to selectively monitor either incoming or outgoing transactions. In another suitable arrangement, the monitor is configured to monitor both incoming and outgoing transactions simultaneously. In one embodiment, the filter module includes a stage comprised of multiple region filters that are adapted to receive pertinent transaction information including the transaction's physical address information. Typically, each of the region filters is associated with a contiguous region of the system's physical address space. In response to receiving the pertinent information, each of the region filters output a signal that indicates whether the transaction fulfills a set of criteria corresponding to the filter. The pertinent information may include, for example, transaction type information and node identification information in addition to the transaction's physical address information. Correspondingly, the criteria for each filter may include transaction type criteria and node identification crit
Brock Bishop Chapman
Chiprout Eli
Elnozahy Elmootazbellah Nabil
Glasco David Brian
Rajamony Ramakrishnan
Jung David
Lally Joseph P.
Salys Casimer K.
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