Efficient hardware handling of positive and negative overflow re

Details Efficient hardware handling of positive and negative overflow re Efficient hardware handling of positive and negative overflow re

1993-12-08

1995-09-05

Envall, Jr., Roy N.

Boots, shoes, and leggings

3647365, G06F 700, G06F 1100

Patent

active

054485096

ABSTRACT:
A computer system provides handling of positive and negative overflow. A first arithmetic operation is performed on a first n-bit unsigned binary operand and a second n-bit signed binary operand to produce an n-bit unsigned binary result. Overflow detection logic circuitry within the arithmetic logic unit detects positive overflow or negative overflow resulting from the arithmetic operation. When there is a positive overflow, saturation logic replaces the output of the two's complement adder with a value of 2.sup.n-1. When there is a negative overflow, the saturation logic replaces the output of the two's complement adder with a value of 0. In an alternate embodiment, a first arithmetic operation is performed on a first n-bit signed binary operand and a second n-bit signed binary operand to produce an n-bit positive signed binary result. For example the arithmetic operation is an addition or subtraction performed by a two's complement adder. In the alternate embodiment, overflow detection logic circuitry within the arithmetic logic unit detects positive overflow or negative overflow resulting from the arithmetic operation. When there is a positive overflow, saturation logic replaces the output of the two's complement adder with a value of 2.sup.n-1 -1. When there is a negative overflow, the saturation logic replaces the output of the two's complement adder with a value of 0.

REFERENCES:
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patent: 4811268 (1989-03-01), Nishitani et al.
patent: 4945507 (1990-07-01), Ishida et al.
patent: 5038313 (1991-08-01), Kojima
patent: 5251166 (1993-10-01), Ishida
Ruby B. Lee, Precision Architecture, IEEE Computer, vol. 22, No. 1, Jan. 1989, pp. 78-91.

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