Efficient hardware divide operation

Details Efficient hardware divide operation Efficient hardware divide operation

2005-09-08

2009-10-06

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07599982

ABSTRACT:
One embodiment of the present invention provides a system that uses the Newton-Raphson technique to perform a division operation. During operation, the system receives a numerator a and a denominator b. The system then divides a by b by first using the Newton-Raphson technique to calculate 1/b, and then multiplying 1/b by a to produce the result a/b. While using Newton-Raphson technique to find 1/b, the system first obtains an initial estimate x0for 1/b and then iteratively solves the equation xi+1=xi(2−bxi). Each iteration involves: (1) using a multiplier circuit to multiply b by xito compute bxi; (2) performing a bit-wise complement operation on bxito compute 2−bxi, whereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation. (3) The system then uses the multiplier circuit to multiply xiby 2−bxito compute xi(2−bxi).

REFERENCES:
patent: 6240433 (2001-05-01), Schmookler et al.
patent: 2003/0149712 (2003-08-01), Rogenmoser et al.
Publication: “Computation of Elementary Functions on the IBM RISC System/6000 Processor”;by P.W. Markstein, IBM J. Res. Develop., vol. 34, No. 1, Jan. 1990, pp. 111-119.

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