Efficient ground noise and common-mode suppression network

Details Efficient ground noise and common-mode suppression network Efficient ground noise and common-mode suppression network

2000-03-20

2002-04-02

Lam, Tuan T. (Department: 2816)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S258000, C327S065000, C327S089000

Reexamination Certificate

active

06366168

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a CMOS differential amplifier. More particularly, the present relates to a CMOS differential amplifier and method embodied therein in which ground noise and common mode suppression are improved.
2. Description of the Related Art
In general, differential amplifiers require the amplification of differential voltages, in the presence of fluctuating common-mode voltages. Since the desired signal is usually the differential voltage, the response to the common-mode signal produces an error at the output that is indistinguishable from the signal.
FIG. 1
is a circuit diagram of a conventional CMOS differential amplifier comprising transistors MN
1
and MN
2
, which are substantially the same size. As shown therein, the differential amplifier comprises a pair of differential inputs V
in1
and V
in2
to transistors MN
1
and MN
2
, respectively. A current source I
1
is connected between V
dd
of a power supply and first terminals of current sources I
2
and I
3
. The other terminal of current source I
2
is connected to the drain of transistor MN
1
, and the other terminal of current source I
3
is connected to the drain of transistor MN
2
. The sources of transistors MN
1
and MN
2
are connected to the other terminal of the power supply.
FIG. 1A
shows the conventional circuit of
FIG. 1
in common mode. In other words, the inputs of transistors MN
1
and MN
2
are connected to a common voltage source. The conventional CMOS differential amplifier is susceptible to insufficient common mode rejection or suppression. The equivalent circuit of
FIG. 1A
is shown in
FIG. 1B
, and the output voltage V
o
is equal to (V
in
−V
T
)·A, where V
T
is the threshold voltage and A is the gain.
FIGS. 2A and 2B
illustrates the differential signal gain response and common-mode gain response, respectively, of the conventional CMOS differential amplifier.
CMOS differential amplifiers are also susceptible to ground noise. Ground noise may be due to, among other factors, digital switching devices inducing currents to the substrate through the depletion capacitances of the device in p-n junctions. In general, the amount of noise injected will be larger the larger the device, and the faster the transients. Argones and Rubio
Experimental Comparison of Substrate Noise coupling Using Different Wafer Types
, IEEE Journal of Solid State Circuits, Vol. 34, No. 10, October 1999 provides a more detailed discussion of substrate (ground) noise, the contents of which are herein incorporated by reference.
FIG. 1C
is a schematic diagram illustrating noise being injected through the ground node.
FIG. 2B
illustrates the response of ground noise gain of the conventional CMOS differential amplifier.
OBJECTS OF THE INVENTION
Therefore, it is an object of the present invention to overcome the aforementioned problems.
It is another object of the present invention to provide a CMOS differential amplifier with improved common mode rejection.
It is a further object of the present invention to provide a CMOS differential amplifier with improved ground noise rejection.
SUMMARY OF THE INVENTION
According to this invention, a CMOS differential amplifier comprises a current supply coupled to a first terminal of a power supply. A first CMOS transistor has a first source, a first drain and a first gate, the first drain being coupled to the current supply. A second CMOS transistor has a second source, a second drain and a second gate, the second drain being coupled to the current supply, and the first and second gates being inputs to the CMOS differential amplifier. A resistance is coupled between a second terminal of the power supply and the first source of the first transistor and the second source of the second transistor.
In accordance with a second aspect of the present invention, the current supply comprises a first current source coupled to the first terminal of the power supply, a second current source coupled to the first current source and the first drain of the first CMOS transistor, and a third current source coupled to the first current source and the second drain of the second CMOS transistor.
In accordance with a third aspect of the present invention, the resistance is greater than 6 ohms.
In accordance with a fourth aspect of the present invention, a method of forming a CMOS differential amplifieri is provided and comprises the step of forming a current supply on a substrate in which the current supply is coupled to a first terminal of a power supply. A first CMOS transistor is formed on the substrate having a first source, a first drain and a first gate, in which the first drain is coupled to the current supply. A second CMOS transistor is formed on the substrate having a second source, a second drain and a second gate, the first and second gates being inputs to the CMOS differential amplifier in which the second drain is coupled to the current supply. A resistance is provided between a second terminal of the power supply and the first source of the first transistor and the second source of the second transistor.
In accordance with a fifth aspect of the present invention, the resistance is selected to be greater than 6 ohms.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.


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patent: 4780687 (1988-10-01), Ducourant
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Schilling et al., “Electronic circuits”, pp. 162-163, 330-339, 1989.*
Aragones et al., “Experimental Comparison of Substrate Noise Coupling Using Different Wafer Types”, IEEE Journal of Solid State Circuits, vol. 34, No. 10, Oct. 1999.
The Circuits and Filters Handbook, edited by Wai-Kai Chen (University of Illinois, Chicago, Illinois), pp. 1509-1570.
http://ece-www.colorado.edu/~bart/book/mintro.htm, by Bart J. Van Zeghbroeck, 1998.

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