Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
1999-12-22
2004-10-05
Tung, Kee M. (Department: 2674)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S502000, C345S505000, C711S169000
Reexamination Certificate
active
06801203
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer graphics technology. More specially, the present invention relates to the design of a graphics pipeline.
2. Related Art
Computer systems are extensively used to perform a wide variety of useful operations in modern society. Applications of computer systems can be found in virtually all fields and disciplines, including but not limited to business, industry, scientific research, education and entertainment. For instance, computer systems are used to analyze financial data, to control industrial machinery, to model chemical molecules, to deliver classroom presentations and to generate special effects for movies. Indeed, it has now come to the point where many of these operations have become so computationally intensive that they cannot be efficiently performed without the help of modern computer systems. As part of the process of performing such operations, computer systems typically utilize some type of display device, such as a cathode ray tube (CRT), a liquid crystal display (LCD) and the like, in order to display images and data which are recognizable to their users. As such, computer systems typically incorporate functionality for generating images and data which are subsequently output to the display device
One technique for generating computer images and viewable data within a computer system is to utilize a graphics pipeline, which uses a series of interconnected functional blocks of circuitry, or “stages”, to render an image. Each stage performs a unique task during each clock cycle. As soon as one stage has completed its task on a pixel, that stage can immediately proceed to work on the next pixel. It does not have to wait for the processing of a prior pixel to complete before it can begin processing the current pixel. More specifically, sets of graphics primitives are specified within the computer system and are subsequently sent down the graphics pipeline. Each stage sequentially performs a different function or functions on the received graphics primitives and then passes that data onto the following stage. Eventually, the graphics pipeline manipulates the graphics primitives in order to produce the final pixel values of an image. Thus, a graphics pipeline enables different graphics data to be processed concurrently, thereby generating graphics images at a higher rate. It should be appreciated that the functionality of a typical prior art graphics pipeline is well known by those of ordinary skill in the art.
However, a typical prior art graphics pipeline does not operate efficiently. More specifically, the memory system used with a typical graphics pipeline inherently has a high memory latency and a high bandwidth. Such a memory system performs optimally when data is bursted in and out of the memory system. Due to this inherent high memory latency, the graphics pipeline often has to wait a long time for requested data to arrive after issuing a memory request. On the other hand, processing in the graphics pipeline cannot proceed until the data is received. As such, the high memory latency adversely impacts the throughput of the graphics pipeline and thus lowers the overall performance of the computer system. As the complexity of graphics applications continue to increase, the performance of computer systems using these prior art graphics pipelines will become even more severely impacted.
Another problem with a typical prior art graphics pipeline is that it uses span traversal during rasterization which causes much unused data to be retrieved, thus resulting in more inefficiency. More particularly, the rasterizer of a typical graphics pipeline traverses the graphics primitives in a span fashion. Unfortunately, span traversal in two-dimensional (2-D) graphics rendering usually results in retrieving a large amount of data that does not end up being used by the pipeline operations. This means that much computing resource is wasted in performing operations that are not useful. Such wasteful use of resource adversely impacts the throughput of the graphics pipeline and thus lowers the overall performance of the computer system.
Thus, there exists a need for a graphics pipeline which does not operate inefficiently due to the high memory latency of the memory system and which does not waste computing resource on operations that are unproductive.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage of the high bandwidth of the memory system while effectively masking the latency of the memory system. More particularly, advantageous reuse of pixel data is enabled by caching, which when combined with data pre-fetching masks the memory latency and delivers high throughput. As such, the present invention provides a novel and superior graphics pipeline over the prior art in terms of more efficient data access and much greater throughput. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
Specifically, in one exemplary embodiment, the present invention is practiced within a computer system having a processor for issuing commands; a memory sub-system for storing information including graphics data; and a graphics sub-system for processing the graphics data according to the commands from the processor. The graphics sub-system comprises a rasterizer for traversing graphics primitives of the graphics data to generate pixel coordinates for pixels corresponding to the graphics primitives; a graphics pipeline for processing the graphics data of the pixels; and a pixel cache for caching the pixel data. Significantly, in this embodiment, the graphics sub-system of the present invention masks the inherent latency of the memory sub-system by pre-fetching the graphics data and storing the graphics data within the pixel cache.
Another embodiment of the present invention includes the above and wherein the graphics sub-system further comprises a pre-fetch queue for storing cache addresses corresponding to the pixels.
Yet another embodiment of the present invention includes the above and wherein the pre-fetch queue is also for storing the pixel coordinates.
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Microsoft Corporation
Monestime Mackly
Tung Kee M.
Woodcock & Washburn LLP
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